NDLI: Low power compression utilizing clock-gating

Content Provider	IEEE Xplore Digital Library
Author	Rajski, J. Moghaddam, E.K. Reddy, S.M.
Copyright Year	2011
Description	Author affiliation: University of Iowa, Department of ECE, Iowa City, IA 52242 (Moghaddam, E.K.; Reddy, S.M.) \|\| Mentor Graphics Corporation, Wilsonville, OR 97070 (Rajski, J.)
Abstract	Growing test data volume and excessive test power consumption in scan testing are both serious concerns for the semiconductor industry. This paper presents a method to simultaneously reduce test data volume and test power utilizing clock gating. This is achieved through not clocking a high proportion of scan chains during both scan shift and test response capture. Reducing the number of scan chains shifted during scan load can be expected to permit higher scan shift frequency thus reducing the test time. Reduced test data volume can be expected to permit fewer tester channels for testing which can increase the number of chips tested in parallel. Experimental results presented for industrial circuits demonstrate that on average a factor of 1.98 and 4 reductions in test data volume and test power, respectively is achievable using the proposed method.
Starting Page	1
Ending Page	8
File Size	364470
Page Count	8
File Format	PDF
ISBN	9781457701535
ISSN	10893539
e-ISBN	9781457701528
DOI	10.1109/TEST.2011.6139145
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-09-20
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Vectors Logic gates Clocks Circuit faults Merging Switches Loading
Content Type	Text
Resource Type	Article
Subject	Applied Mathematics Electrical and Electronic Engineering

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