NDLI: Activity-Driven Fine-Grained Clock Gating and Run Time Power Gating Integration

Content Provider	IEEE Xplore Digital Library
Author	Li Li Ken Choi Haiqing Nan
Copyright Year	1993
Abstract	As the two most widely used techniques to reduce dynamic power and leakage power, clock gating (CG) and power gating (PG), respectively, are expected to be integrated together effectively. Normally, the implementation of CG leads to some redundant operations, which provides the opportunity to apply PG. In this brief, we have proposed an activity-driven fine-grained CG and PG integration. First, we introduce an optimized bus-specific-clock-gating (OBSC) scheme to improve traditional XOR-based CG. It chooses only a subset of flip-flops (FFs) to be gated selectively, and the problem of gated FF selection is reduced from exponential complexity into linear. Then those combinational logics, which completely depend on the outputs of gated FFs, are performing redundant operations. They can be power gated, and the clock enable signal generated by OBSC is used as the sleep signal. A minimum average idle time concept is proposed to determine whether the insertion of PG will lead to energy reduction. In order to evaluate our technique, we experimented on twenty ISCAS'89 circuits. The simulation results show that 25.07% dynamic power can be reduced by OBSC, and 50.19% active leakage power can be saved by PG.
Sponsorship	IEEE Computer Society Association for Computing Machinery (ACM)/SIGDA IEEE Computer Society Technical Committee on Design Automation
Starting Page	1540
Ending Page	1544
Page Count	5
File Size	363868
File Format	PDF
ISSN	10638210
Volume Number	21
Issue Number	8
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-08-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Logic gates Clocks Estimation Very large scale integration Integrated circuit modeling CMOS integrated circuits Latches power gating Clock gating low power
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Software Hardware and Architecture

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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