NDLI: Challenges and best practices in advanced silicon debug

Content Provider	IEEE Xplore Digital Library
Author	Zeng, Jing
Copyright Year	2011
Description	Author affiliation: MediaTek (Zeng, Jing)
Abstract	Which is better for the debug of root causes for post-silicon issues with functionality, performance, or power: functional test on ATE, system-level test, or structural test? The panel will discuss pros and cons of the different approaches. Functional or system tests have traditionally been used for debugging functionality, performance and power related issues for high performance microprocessors or complex Systems-on-Chip. The functional approach can be expensive in infrastructure investment and in resources. Much of the infrastructure may not be usable from product to product. Results may not provide all the information for an effective post-silicon design optimization strategy. Structural tests such as scan or different forms of BIST can provide greater coverage, but does not know if a design is correct. Scan-based tests can be used for performance debug and is easier to automate. Scan takes advantage of existing architectures in a design and the automated test pattern generation process. Due to the limited number of at-speed capture cycles, scan tests can be easier to debug as more information of the chip behavior at the point of failure is available. However, scan can also test non-functional paths or easily generate over-kill or over stress conditions. How can scan be used if it can cause a false performance issue? Diagnosing power related issues can be a complex problem. Besides characterizing the power consumption during system testing, parametric tests and test-structure assisted test-based learning often could provide a quick read into potential power issues. The panel will analyze pro's and con's of various types and combinations of advance silicon debug to highlight the challenges and best practices available. Panelists represent years of experience in Silicon debug in Chip, Board, and System test and debug as well as EDA.
Starting Page	1
Ending Page	1
File Size	39048
Page Count	1
File Format	PDF
ISBN	9781457701535
ISSN	10893539
e-ISBN	9781457701528
DOI	10.1109/TEST.2011.6139193
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-09-20
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Content Type	Text
Subject	Applied Mathematics Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

How can the results of silicon debug justify the investment in design-for- debug infrastructure?

How can the results of silicon debug justify the investment in design-for- debug infrastructure?

A silicon validation and debug solution with great benefits and low costs

Design-for-debug to address next-generation soc debug concerns

On efficient silicon debug with flexible trace interconnection fabric

Facilitating rapid first silicon debug

Are Design for Debug (DFD) Features that are Put in Reuse Cores Sufficient for Silicon Debug? - position statement

SoC and Multi-Core Debug: Are Design for Debug (DFD) features that are put in reuse cores sufficient for Silicon Debug?

SOC and Multi-Core Debug: Are Design for Debug (DFD) features that are put in reuse cores sufficient for Silicon Debug?

Challenges and best practices in advanced silicon debug

Similar Documents

How can the results of silicon debug justify the investment in design-for- debug infrastructure?

How can the results of silicon debug justify the investment in design-for- debug infrastructure?

A silicon validation and debug solution with great benefits and low costs

Design-for-debug to address next-generation soc debug concerns

On efficient silicon debug with flexible trace interconnection fabric

Facilitating rapid first silicon debug

Are Design for Debug (DFD) Features that are Put in Reuse Cores Sufficient for Silicon Debug? - position statement

SoC and Multi-Core Debug: Are Design for Debug (DFD) features that are put in reuse cores sufficient for Silicon Debug?

SOC and Multi-Core Debug: Are Design for Debug (DFD) features that are put in reuse cores sufficient for Silicon Debug?

Challenges and best practices in advanced silicon debug