NDLI: Design of signature circuits based on weight distributions of error-correcting codes

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Design of signature circuits based on weight distributions of error-correcting codes

Content Provider	IEEE Xplore Digital Library
Author	Iwasaki, K. Yamaguchi, N.
Copyright Year	1990
Description	Author affiliation: Hitachi Ltd., Tokyo, Japan (Iwasaki, K.; Yamaguchi, N.)
Abstract	Design techniques that can improve the aliasing probabilities of signature circuits for VLSI BIST (built-in self-test) are presented. The proposed techniques are based on the binary weight distributions of error-correcting codes over GF(2) and GF(2/sup m/). The technique considered for calculating the aliasing probability of signature circuits is appropriate for a vector supercomputer. Some of the calculations were done using the S810 supercomputer. The vectorization ratio of the program was 99.885% for an MISR (multiple-input signature register) with 16 inputs and for test length n=100-105.
Starting Page	779
Ending Page	785
File Size	641533
Page Count	7
File Format	PDF
ISBN	081869064X
DOI	10.1109/TEST.1990.114095
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1990-09-10
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Error correction codes Polynomials Circuit testing Probability Very large scale integration Built-in self-test Supercomputers Automatic testing Laboratories Vectors
Content Type	Text
Resource Type	Article

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