NDLI: Event qualification: a gateway to at-speed system testing

Content Provider	IEEE Xplore Digital Library
Author	Whetsel, L.
Copyright Year	1990
Description	Author affiliation: Texas Instrum. Inc., Plano, TX, USA (Whetsel, L.)
Abstract	The author describes an event qualification architecture that can be designed into ICs to provide the timing and control required to activate an IC's test logic effectively during normal system operation. The proposed approach combines boundary test logic with a patented event qualification (EQUAL) architecture that can be incorporated into IC designs. While the EQUAL architecture can be used to control a variety of different IC test structures, combining it with boundary test logic is ideal for testing at-speed data transfers between ICs on a board design. EQUAL's ability to enable boundary test logic to capture at-speed data transfers between ICs allows testing for timing-sensitive and/or intermittent failures that may occur during system operation. The capabilities described here are based on results from an experiment in which a board was designed with prototype ICs that include boundary test logic and EQUAL architecture. Experimental results showed that the approach allowed meaningful at-speed test data to be obtained nonintrusively from an operating circuit board, using only scan access to set up the test and extract the results.
Starting Page	135
Ending Page	141
File Size	694870
Page Count	7
File Format	PDF
ISBN	081869064X
DOI	10.1109/TEST.1990.114011
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1990-09-10
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Qualifications System testing Logic testing Circuit testing Logic design Integrated circuit testing Timing Control systems Prototypes Printed circuits
Content Type	Text
Resource Type	Article

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