NDLI: A high-speed pin-memory architecture using multiport dynamic RAMs

Content Provider	IEEE Xplore Digital Library
Author	Tsai, S.-J. Lee, W.-J.
Copyright Year	1990
Description	Author affiliation: AT&T Bell Lab., Princeton, NJ, USA (Tsai, S.-J.)
Abstract	The authors describe a novel pin-memory design based on multiport dynamic video RAMs (VRAMs). Each pin (or channel) has a 512 K pattern depth allows a 100-MHz vector rate, and is economical in both size (3*1.5 in) and cost (less than $100). These achievements were made possible by a VRAM-oriented pin-memory architecture and the associated memory control circuitry, which are instrumental in facilitating the following features: the arbitration of the read/write and refresh operations, the coordination of two processors that access the memory at different stages of a test cycle, the provision for as many pins as possible to share components to reduce the overall cost and space, and the preservation of the independence of an individual pin so that it can be either active or idle for a particular burst regardless of the status of the others. The design described has been fully implemented in the High Speed Test System (HSTS) and functions successfully.
Starting Page	347
Ending Page	354
File Size	655776
Page Count	8
File Format	PDF
ISBN	081869064X
DOI	10.1109/TEST.1990.114041
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1990-09-10
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit testing Costs Random access memory Pins Read-write memory Permission System testing Computer peripherals Research and development Power generation economics
Content Type	Text
Resource Type	Article

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