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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Flint, A. |
| Copyright Year | 1995 |
| Description | Author affiliation: Semicond. Products Sector, Motorola Inc., Tempe, AZ, USA (Flint, A.) |
| Abstract | The secret to successfully testing MCM prototype products is to perform the right amount of testing. Attempting to test every transistor inside of each chip in the MCM is likely to result in a failed project, because most MCMs are too complex to test as though they are one large IC. The formula used for several successful projects was to (1) obtain functional ICs, (2) devise tests that verify the ICs are properly interconnected, and (3) run some simple functional tests to verify the MCM performs properly as a unit. Obtaining good chips is usually not a big problem, since most IC manufacturers perform relatively complete testing of the bare ICs. Generating interconnect tests is a straightforward task for many designs. Sometimes design-for-testability (DFT) is required to make the design more readily testable. Functional tests, even very limited ones, are best developed using logic simulation, allowing coverage and correctness to be verified before going to the tester. A brief sampling is presented of specific approaches to consider when planning the strategy. |
| File Size | 96952 |
| File Format | |
| ISBN | 0780329929 |
| ISSN | 10893539 |
| DOI | 10.1109/TEST.1995.529896 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1995-10-21 |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Integrated circuit testing Circuit testing Circuit faults Dictionaries Semiconductor device testing Performance evaluation Integrated circuit interconnections Logic testing Strategic planning System testing |
| Content Type | Text |
| Resource Type | Article |
| Subject | Applied Mathematics Electrical and Electronic Engineering |
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