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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Frisch, A. Aigner, M. Almy, T. Greub, H. Hazra, M. Mohr, S. Naclerio, N. Russell, W. Stebnisky, M. |
| Copyright Year | 1995 |
| Description | Author affiliation: Tektronix Inc., Beaverton, OR, USA (Frisch, A.; Aigner, M.; Almy, T.) |
| Abstract | A ready supply of high quality Known Good Die (KGD) is essential for obtaining acceptable Multi-Chip Module (MCM) yields and reducing costs. Unfortunately, the testers needed for testing and screening VLSI chips to supply high quality KGD are quite expensive, especially for high speed or high pin count ICs. In addition, there are issues connected with testing accuracy-the tester environment may limit performance testing because of interconnect length and capacitance, and with burn-in-which may require temporary packaging of die. Building special test equipment is only cost effective if production volumes are large. Hence, a low cost alternative for at-speed testing that yields high quality die is needed to drive down the cost of low volume or prototype MCMs. This paper describes a double-blind experiment devised to prove the viability of a KGD methodology based upon wafer level test-using embedded performance testing circuits-and wafer level burn-in. |
| Starting Page | 328 |
| Ending Page | 335 |
| File Size | 692010 |
| Page Count | 8 |
| File Format | |
| ISBN | 0780329929 |
| ISSN | 10893539 |
| DOI | 10.1109/TEST.1995.529857 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1995-10-21 |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Costs Circuit testing Software testing Silicon Timing Contracts Probes System testing Integrated circuit interconnections Test equipment |
| Content Type | Text |
| Resource Type | Article |
| Subject | Applied Mathematics Electrical and Electronic Engineering |
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