NDLI: IDDQ testing of CMOS opens: an experimental study

Content Provider	IEEE Xplore Digital Library
Author	Singh, A.D. Rasheed, H. Weber, W.W.
Copyright Year	1995
Description	Author affiliation: Dept. of Electr. Eng., Auburn Univ., AL, USA (Singh, A.D.; Rasheed, H.)
Abstract	IDDQ testing is known to be very effective in detecting shorts in CMOS circuits. It has also been reported that open defects that lead to "floating" transistor gates can also be detected if the gate acquires a sufficient voltage to leak measurable current. Recent experiments evaluating a new on-chip IDDQ sensor indicated the possibility of additional detection mechanisms for other types of open failures, including open source and drain connections. To investigate this in more detail, we designed and fabricated two test chips in CMOS technology containing the 74181 ALU circuit. Our test chips include the capability of replacing, one at a time, individual cells in the 74181 circuits with back up cells that each contain a single open defect. In this way in addition to the fault free circuits, a total of 59 faulty circuits can be configured, each containing a different open defect. It was found that IDDQ testing with random vectors detected 48 of the 59 open defects. Analysis of the experimental data reveals new mechanisms that explain the detection of floating gate and open source and drain failures.
Starting Page	479
Ending Page	489
File Size	981805
Page Count	11
File Format	PDF
ISBN	0780329929
ISSN	10893539
DOI	10.1109/TEST.1995.529875
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1995-10-21
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit testing Circuit faults CMOS technology Fault detection Logic testing Voltage Bridge circuits Power supplies Rails Leak detection
Content Type	Text
Resource Type	Article
Subject	Applied Mathematics Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A MIXED FUNCTIONAL/IDDQ TESTING METHODOLOGY FOR CMOS TRANSISTOR FAULTS

Detection of undetectable faults using IDDQ testing

An IDDQ sensor circuit for low-voltage ICs

Very-low-voltage testing for weak CMOS logic ICs

Testing for floating gates defects in CMOS circuits

Constraints for using IDDQ testing to detect CMOS bridging faults

Fault coverage analysis for physically-based CMOS bridging faults at different power supply voltages

IDDQ defect detection in deep submicron CMOS ICs

IDDQ testing in low power supply CMOS circuits

IDDQ testing of CMOS opens: an experimental study

Similar Documents

A MIXED FUNCTIONAL/IDDQ TESTING METHODOLOGY FOR CMOS TRANSISTOR FAULTS

Detection of undetectable faults using IDDQ testing

An IDDQ sensor circuit for low-voltage ICs

Very-low-voltage testing for weak CMOS logic ICs

Testing for floating gates defects in CMOS circuits

Constraints for using IDDQ testing to detect CMOS bridging faults

Fault coverage analysis for physically-based CMOS bridging faults at different power supply voltages

IDDQ defect detection in deep submicron CMOS ICs

IDDQ testing in low power supply CMOS circuits

IDDQ testing of CMOS opens: an experimental study