NDLI: High-level implementation of the 5-stage pipelined ARM9TDM core

Content Provider	IEEE Xplore Digital Library
Author	Arandilla, C.C. Constantino, J.B.A. Glova, A.O.M. Ballesil-Alvarez, A.P. Reyes, J.A.P.
Copyright Year	2010
Description	Author affiliation: Intel Microprocessors Laboratory, Microelectronics and Microprocessors Laboratory, Electrical and Electronics Engineering Institute, University of the Philippines - Diliman (Arandilla, C.C.; Constantino, J.B.A.; Glova, A.O.M.; Ballesil-Alvarez, A.P.; Reyes, J.A.P.)
Abstract	This paper summarizes a project on the implementation of the ARM9TDM, a 32-bit RISC processor based on the ARM9TDMI. This core is the successor to the ARM7TDMI-S which is used for embedded applications requiring low power, small chip area, and high processing speed. The main features of the ARM9TDM are its use of a 5-stage pipelined datapath and a Harvard architecture that has separate data and instruction interfaces. It supports the ARMv4T instruction set architecture (ISA) that uses both the 32-bit ARM instructions and 16-bit Thumb instructions. It includes a high-speed multiplier and debug capabilities using JTAG boundary scan test interface. It does not include an EmbeddedICE-RT module. The project was coded using the Verilog Hardware Description Language and was simulated using Synopsys VCS. The verified code was synthesized in 0.25-micrometer standard cells using Synopsys Design Vision. The layout generated by Synopsys Astro was characterized as having a maximum operating frequency of 34.13 MHz, an average power consumption of 16mW and a chip size of 1.5335 sq. mm.
Starting Page	1696
Ending Page	1700
File Size	667483
Page Count	5
File Format	PDF
ISBN	9781424468898
e-ISBN	9781424468904
DOI	10.1109/TENCON.2010.5686046
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-11-21
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Registers Pipelines Clocks Power demand Thumb Hazards Computer architecture debugging ARM9 ARMv4T RISC Processor 5-Stage Pipeline Harvard Architecture coprocessor interface
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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