NDLI: A power-gatable reconfigurable logic chip with FeRAM cells

Content Provider	IEEE Xplore Digital Library
Author	Koga, M. Iida, M. Amagasaki, M. Ichida, Y. Saji, M. Iida, J. Sueyoshi, T.
Copyright Year	2010
Description	Author affiliation: LSI Development Headquarters, ROHM Co., Ltd., 2-4-8 Shinyokohama, Kouhoku-ku, Yokohama 222-8575, Japan (Iida, J.) \|\| Graduate School of Science and Technology, Kumamoto University, 2-39-1 Kurokami, Kumamoto 860-8555, Japan (Koga, M.; Iida, M.; Amagasaki, M.; Sueyoshi, T.) \|\| KTC LSI Development Headquarters, ROHM Co., Ltd., 21 Saiin Mizosaki-cho, Ukyo-ku, Kyoto 615-8585, Japan (Ichida, Y.; Saji, M.)
Abstract	An advantage of a RLD (Reconfigurable logic device) such as an FPGA (Field programmable gate array) is that it can be customized after being manufactured. However, there is a problem related to standby power when using SRAM as a configuration memory. Power gating, which is one of the power reduction techniques, is difficult to use in SRAM-based RLDs because of the high overhead — data hibernation and reconfiguration time — and SRAM being volatile. In this paper, we describe a chip that we developed — a reconfigurable logic chip based on FeRAM (Ferroelectric random access memory) technology. The chip employs island-style routing architecture and uses a variable grain logic cell as a logic block. A NV-FF (Non-Volatile FlipFlop), which contains FeRAM, a FF, and power-gating control circuits, is used as configuration memory. The NV-FF can transmit data between FeRAM and FF automatically when power to the chip is turned off/on. Thus, chip-level power gating is possible. The hibernate/restore time is less than I ms. The chip has 18 × 18 logic blocks and an area of 54.76 $mm^{2}.$ We also make test circuits for testing the chip after fabrication. Target fault model is Stack-at faults model. When we merge all 28 circuits, fault coverage is 78 %.
Starting Page	317
Ending Page	322
File Size	1433878
Page Count	6
File Format	PDF
ISBN	9781424468898
e-ISBN	9781424468904
DOI	10.1109/TENCON.2010.5686019
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-11-21
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Clocks Nonvolatile memory Random access memory Logic gates Ferroelectric films Routing Timing
Content Type	Text
Resource Type	Article

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