NDLI: Atto Joule CMOS gates using reversed sizing and W/L swapping

Content Provider	IEEE Xplore Digital Library
Author	Beg, A. Beiu, V. Ibrahim, W.
Copyright Year	2011
Description	Author affiliation: Faculty of Information Technology United Arab Emirates University Al-Ain, United Arab Emirates (Beg, A.; Beiu, V.; Ibrahim, W.)
Abstract	Voltage reduction is a very widely used low-power technique (as reducing dynamic power quadratically, and leakage power linearly) which does sacrifice performance. An alternate technique, which is much less explored/investigated, is to rely on currents instead. The paper presents a thorough but still preliminary comparison of a recently introduced CMOS design technique which limits/reduces currents, with both the conventional/classical CMOS design, and also with a fresh sub-threshold CMOS design specifically aimed for ultra-low power (ULP). The preliminary results reported here suggest that the new design could achieve: (i) significantly lower power than classical CMOS (20–60×) without drastically degrading performances (5–20×); (ii) much better performances (100–200×) than the ULP scheme considered at power levels which are manageable (10–40x); while (iv) surpassing both of them on power-delay-product (PDP) and energy-delay-product (EDP). In particular, our inverters in 16nm are able to break the atto-Joule barrier at 300mV, and exhibit a delay of about 9ns.
Starting Page	498
Ending Page	501
File Size	160514
Page Count	4
File Format	PDF
ISBN	9781612841359
e-ISBN	9781612841373
DOI	10.1109/NEWCAS.2011.5981328
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-06-26
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Inverters CMOS integrated circuits Transistors Threshold voltage Delay Logic gates CMOS technology
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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