NDLI: An ultra high-speed, mixed-signal emulator for solving power system dynamic equations

Content Provider	IEEE Xplore Digital Library
Author	Fabre, L. Lanz, G. Nagel, I. Conte, F.L. Cherkaoui, R. Kayal, M.
Copyright Year	2011
Description	Author affiliation: Electronics Laboratory & Power Systems Laboratory, Ecole Polytechnique Fédérale de Lausanne, Switzerland (Fabre, L.; Lanz, G.; Nagel, I.; Conte, F.L.; Cherkaoui, R.; Kayal, M.)
Abstract	This paper focuses on a new pipelined processing unit architecture dedicated to mixed-signal power system emulation. Prior research in this field has proven that analog emulation overcomes the speed limits of numerical simulators with reliable accuracy. Then, a new concept based on field programmable power network system (FPPNS) has been developed in order to gain in term of flexibility. It is based on a hybrid architecture where grid equations are solved analogically and generator and load equations are solved digitally. A first platform based on a developed application specific integrated circuit has validated the concept with a 16-node topology. The present work aims to extend the size of the emulation hardware (up to 100 nodes) as well as to increase the speed. Therefore the digital equations are solved on an embedded FPGA containing four parallel pipelined processing unit which are interfaced to the analog emulator. Speed results are provided and compared with a reference numerical simulator.
Starting Page	374
Ending Page	377
File Size	362567
Page Count	4
File Format	PDF
ISBN	9781612841359
e-ISBN	9781612841373
DOI	10.1109/NEWCAS.2011.5981248
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-06-26
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Mathematical model Generators Power system dynamics Emulation Equations Computer architecture Clocks
Content Type	Text
Resource Type	Article

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