NDLI: Offset-corrected 5GHz CMOS dynamic comparator using bulk voltage trimming: Design and analysis

Content Provider	IEEE Xplore Digital Library
Author	Yongsheng Xu Belostotski, L. Haslett, J.W.
Copyright Year	2011
Description	Author affiliation: Electrical and Computer Engineering Department, University of Calgary, Canada (Yongsheng Xu; Belostotski, L.; Haslett, J.W.)
Abstract	This paper presents an improved two-stage dynamic comparator using a bulk voltage trimming technique for offset calibration. The comparator requires only a one-phase clock while exerting no extra load on the first stage, leading to higher operating speed. The calibration does not require any extra power supply and does not consume any quiescent current, while increasing the offset calibrating range by a factor of 2 over previous techniques. Detailed analysis of the method of calibrating both stages of the dynamic comparator is provided. Simulation results in a 65nm digital CMOS process show that the comparator is capable of working at a speed of 5GHz with 90uW of power consumption from a 1V power supply, achieving an input-referred offset calibrating range of ±35mV at ∼±2.3mV/step at the typical-typical process corner.
Starting Page	277
Ending Page	280
File Size	854173
Page Count	4
File Format	PDF
ISBN	9781612841359
e-ISBN	9781612841373
DOI	10.1109/NEWCAS.2011.5981309
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-06-26
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Calibration Clocks Threshold voltage Capacitors Mathematical model MOSFETs
Content Type	Text
Resource Type	Article

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