NDLI: Virtual design for technology exploration - a process design integration methodology for a fabless entity -

Content Provider	IEEE Xplore Digital Library
Author	Chun, C. Corleto, J. Nowak, M. Radojcic, R.
Copyright Year	2008
Description	Author affiliation: Qualcomm CDMA Technol., San Diego, CA (Chun, C.; Corleto, J.; Nowak, M.; Radojcic, R.)
Abstract	The challenges of deriving early-adopter competitive advantage, even with fabless access to process technology, through leveraging features offered by the advanced, and possibly disruptive, process technologies in real SoC products, are outlined. A structured methodology for addressing these challenges, and bridging the gap between process and design, sufficiently early in the development cycle to allow co-optimization all the way up to the architecture level, is proposed. A virtual design flow of a potential product that allows rapid estimation of performance, power and cost attributes, as a function of a given set of process or design assumptions is proposed. Key features of such a virtual flow, and a summary of the attributes of several candidate point tools is presented. The accuracy requirements of the dasiapredictivepsila models required to enable this flow are assessed and discussed. A few example applications of the proposed methodology are presented to illustrate the use model, to define the required attributes of the virtual design flow, and to contrast this concept versus use of spreadsheets on one hand, or use of traditional design flows on the other.
Starting Page	125
Ending Page	130
File Size	326814
Page Count	6
File Format	PDF
ISBN	9781424418107
DOI	10.1109/ICICDT.2008.4567261
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-06-02
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Process design Phase change random access memory Cost function Predictive models Design methodology Prediction methods System analysis and design Technology forecasting Packaging FinFETs Technology assessment
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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