NDLI: How does inversed temperature dependence affect timing sign-off

Please wait, while we are loading the content...

2015 International Conference on IC Design & Technology (ICICDT)

2014 IEEE International Conference on IC Design & Technology

Proceedings of 2013 International Conference on IC Design & Technology (ICICDT)

2012 IEEE International Conference on IC Design & Technology

2011 IEEE International Conference on IC Design & Technology

2010 IEEE International Conference on Integrated Circuit Design and Technology

2009 IEEE International Conference on IC Design and Technology

2008 IEEE International Conference on Integrated Circuit Design and Technology and Tutorial

2008 IEEE International conference on Integrated Circuit Design and Technology

Proceedings 2008 IEEE International conference on Integrated Circuit Design and Technology [Front matter]

ICICDT Tutorials

A futur view of SoC in the post 45nm era

Synergy between design and process: A key factor in the evolving microelectronic landscape

Plenary & workshop sessions

Table of content

2008 IEEE International conference on Integrated Circuit Design and Technology

Silicon-On-Nothing (SON) applications for Low Power technologies

Evaluation of Ultra Thin Body Si-On-ONO (UTB SOONO) transistors using ultra thin spacer technology

New charge trapping phenomena in Recessed-Channel-Array-Transistor (RCAT) after Fowler-Nordheim stress

Use of the p-floating shielding layer for improving electric field concentration of the recessed gate

CMOS SOI technology for WPAN. Application to 60 GHz LNA

A 0.5 V area-efficient transformer folded-cascode low-noise amplifier in 90 nm CMOS

A low power multi-band selector DLL with wide-locking range

Design of a current steering CMOS D/A converter with an adaptive control switch and a novel layout technique

3D-structured on-chip buck converter for distributed power supply system in SiPs

A Localized Power Control mixing hopping and Super Cut-Off techniques within a GALS NoC

Improvement of power supply rejection ratio of LDO deteriorated by reducing power consumption

An innovative sub-32nm SRAM current sense amplifier in double-gate CMOS insensitive to process variations and transistor mismatch

SRAM memory cell leakage reduction design techniques in 65nm low power PD-SOI CMOS

Which is the best dual-port SRAM in 45-nm process technology? — 8T, 10T single end, and 10T differential —

Low-voltage 6T FinFET SRAM cell with high SNM using HfSiON/TiN gate stack, fin widths down to 10nm and 30nm gate length

Independent-gate four-terminal FinFET SRAM for drastic leakage current reduction

A study of L effects in a 40 nm SA-MSCFET

A new edge termination technique to improve voltage blocking capability and reliability of field limiting ring for power devices

An SOI-based self-aligned quasi-SOI MOSFET with π-shaped semiconductor conductive layer

Reliability of advanced embedded non-volatile memories: The 2T-FNFN device

SOI chip design and charging damage

TDDB and BTI reliabilities of high-k stacked gate dielectrics - Impact of initial traps in high-k layer -

Reliability issues for nano-scale CMOS dielectrics: - From transistors to product reliability - - From SiON to high-k dielectrics -

Threshold voltage shift instability induced by plasma charging damage in MOSFETs with high-k dielectric

Analysis of Si substrate damage induced by inductively coupled plasma reactor with various superposed bias frequencies

Metal gate effects on a 32 nm metal gate resistor

Design of a 6-bit 1GSPS fully folded CMOS A/D converter for Ultra Wide Band (UWB) applications

An integrated class D audio amplifier based on sliding mode control

Comparative analysis of two operational amplifier topologies for a 40MS/s 12-bit pipelined ADC in 0.35μm CMOS

Virtual design for technology exploration - a process design integration methodology for a fabless entity -

Technology development driven by design

A low power 12-bit and 30-MS/s pipeline analog to digital converter in 0.35μm CMOS

Sleep circuit for SRAM core with improved noise-margin

Low power clocking strategies in deep submicron technologies

Energy delay optimization methodology for current-mode signaling for on-chip interconnects

Overview of DFT features of the Sun Microsystems Niagara2 CMP/CMT SPARC chip

Energy-efficient and metastability-immune timing-error detection and recovery circuits for dynamic variation tolerance

Process variability-induced timing failures— A challenge in nanometer CMOS low-power design

Ring oscillator circuit structures for measurement of isolated NBTI/PBTI effects

A comparative study of variability impact on static flip-flop timing characteristics

Analysing the effect of process variation to reduce parametric yield loss

Low-voltage limitations and challenges of nano-scale CMOS LSIs - A personal view of memory designer -

New writing mechanism for reliable SONOS embedded memories with thick tunnel oxide

Read and write circuit assist techniques for improving Vccmin of dense 6T SRAM cell

The future of flash memory: Is floating gate technology doomed to lose the race?

SONOS memories with embedded silicon nanocrystals in nitride by in-situ deposition method

Temperature-based phase change memory model for pulsing scheme assessment

Ultra-high bandwidth memory with 3D-stacked emerging memory cells

Transconductance enhancement of Si nanowire transistors by oxide-induced strain

A new analytical model for predicting SWCNT band-gap from geometrical properties

Probabilistic modeling of nanoscale adder

Building a reliable internet core using soft error prone electronics

Real-time neutron and alpha soft-error rate testing of CMOS 130nm SRAM: Altitude versus underground measurements

Traces of errors due to single ion in floating gate memories

3D Contactless communication for IC design

Integration of SAW filters

Dynamic measurement of critical-path timing

Key considerations given to the design of a next generation multi-core communications platform

On-chip circuit for measuring jitter and skew with picosecond resolution

New state variable device opportunities for beyond CMOS: A system perspective

3D multichannels and stacked nanowires technologies for new design opportunities in nanoelectronics

Device architectures based on graphene channels

A simple compact model to analyze the impact of ballistic and quasi-ballistic transport on ring oscillator performance

A 3-tier, 3-D FD-SOI SRAM macro

3D CMOS integration: Introduction of dynamic coupling and application to compact and robust 4T SRAM

A generic method for variability analysis of nanoscale circuits

Stochastic analysis for crosstalk noise of coupled interconnects with process variations

A novel moment-based methodology for accurate and efficient static timing analysis

How does inversed temperature dependence affect timing sign-off

Statistical leakage modeling in CMOS logic gates considering process variations

Design of ST planar integrated inductors based on INFINISCALE flow

2007 IEEE International Conference on Integrated Circuit Design and Technology

2006 IEEE International Conference on IC Design and Technology

2005 International Conference on Integrated Circuit Design and Technology, 2005. ICICDT 2005.

2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)

How does inversed temperature dependence affect timing sign-off

Content Provider	IEEE Xplore Digital Library
Author	Wu, S.H. Tetelbaum, A. Wang, L.-C.
Copyright Year	2008
Description	Author affiliation: LSI Corp., Milpitas, CA (Wu, S.H.; Tetelbaum, A.)
Abstract	As mainstream processing technology advances into 65 nm and beyond, many factors that were previously considered secondary or insignificant, can now have an impact on chip timing. One of these factor is inversed temperature dependence (ITD). As supply voltage continues scaling into sub-IV territory, delay-temperature relationship can be reversed on some cells, meaning that device switching time may decrease as temperature increases. ITD posts a new challenge for timing sign-off because the highest and lowest sign-off temperatures may no longer be the worst-case and best-case timing corners. This work discuss the effect of ITD and its implication on timing sign-off, based on a standard cell library used in a typical design flow.
Starting Page	297
Ending Page	300
File Size	308628
Page Count	4
File Format	PDF
ISBN	9781424418107
DOI	10.1109/ICICDT.2008.4567300
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-06-02
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Temperature dependence Timing Temperature sensors Libraries Low voltage Large scale integration Delay effects Circuits Propagation delay Electron mobility
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in