NDLI: A futur view of SoC in the post 45nm era

Content Provider	IEEE Xplore Digital Library
Author	Ko, Uming
Copyright Year	2008
Description	Author affiliation: TI, USA (Ko, Uming)
Abstract	While the semiconductor industry has delivered tremendous advancements over the years, the 45nm process node era is still in its infancy with only ≪20% of the market actually utilizing this process node by 2010. There are still many, many more benefits to be realized from 45nm technology. Over the last two decades of semiconductor process technology advancements, the electronics industry has enjoyed continuous improvements in performance, reduction in power and reduction in die size. And, these trends are expected to continue into the future as the industry moves into 45nm and beyond. Dr. Uming Ko, Senior Fellow and Director of Wireless Chip Technology Center from Texas Instrument’s will talk about the future trends expected in the post 45nm era of process technology, continued improvements in performance, power and size. He will also assess the characteristics of different end products such as wireless handsets, advanced imaging and surveillance and medical electronics, to determine which semiconductor products and markets might be good candidates for driving advanced process nodes. Advanced process nodes beyond 45nm will continue to deliver the types of advancements we’ve experienced historically; however going forward there is an increasing need to assess which products make sense for advanced nodes regardless of what is technically feasible. Dr. Ko will evaluate SoC trends going forward and will discuss the broader, market-based considerations for technology decisions in the post 45nm era.
File Size	89905
File Format	PDF
ISBN	9781424418107
DOI	10.1109/ICICDT.2008.4567226
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-06-02
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Microelectronics Circuits Research and development Research and development management Silicon Electronics industry Process design Pattern matching Energy consumption Error analysis
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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