NDLI: Effects of detailed substrate modeling and solder layout design on the $1^{st}$ and $2^{nd}$ level solder joint reliability for the large die FCBGA

Content Provider	IEEE Xplore Digital Library
Author	Biswas, K. Shiguo Liu Xiaowu Zhang Chai, T.C.
Copyright Year	2008
Description	Author affiliation: IBIDEN Singapore Pte Ltd., Singapore (Biswas, K.; Shiguo Liu)
Abstract	This paper discusses the thermo-mechanical design and analysis of a large die FCBGA. This work focuses on co-design of the $1^{st}$ level and $2^{nd}$ level solder joint reliability analysis of a flip chip package emphasizing the effect of details substrate modeling and solder layout design. Model with all the layered structures for the build up substrate is compared with the compact model of equivalent substrate. The fatigue life of the $2^{nd}$ level solder joint is estimated by the Darveaux's method. Inelastic strain energy density per cycle accumulated in the solder bumps during thermal cycling is used to predict the trend of fatigue life for the $1^{st}$ level bumps. Effects of die thickness, substrate thickness and heat spreader on solder fatigue life are analyzed. As the maximum inelastic strain energy density occurs at the solder ball near the die edge, different solder ball layouts are studied by changing the distance of the critical solder ball from die edge. In addition, to further improve the packaging design of large die FCBGA, the fatigue life of most critical solder ball is investigated by means of the design of experiment (DOE). The final results could be used as a design guideline to improve the fatigue life of both the $1^{st}$ and $2^{nd}$ level solder joints of the package.
Starting Page	1
Ending Page	7
File Size	1265070
Page Count	7
File Format	PDF
ISBN	9781424421275
DOI	10.1109/ESIME.2008.4525051
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-04-20
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Soldering Fatigue Flip chip Electronics packaging Thermal conductivity Capacitive sensors Conducting materials Finite element methods Solid modeling Microelectronics
Content Type	Text
Resource Type	Article

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