NDLI: Correlating drop impact simulations with drop impact testing using high-speed camera measurements

Content Provider	IEEE Xplore Digital Library
Author	Zaal, J.J.M. van Driel, W.D. Kessels, F.J.H. Zhang, G.Q.
Copyright Year	2008
Description	Author affiliation: Delft Univ. of Technol., Delft (Zaal, J.J.M.; van Driel, W.D.)
Abstract	The increased use of mobile appliances in today's society has resulted in an increase of reliability issues related to drop performance. Mobile appliances are dropped multiple times during their lifespan and the product is required to survive common drop accidents. The use of lead-free solder compositions and the decreasing size of microelectronics aggravated the sensitivity of these products towards drop failures. Also, the use of miniature IC packages like Wafer Level Chip Scale Packages (WLCSP) with smaller lead sizes resulted in a decreased amount of material available to absorb the loading caused by a drop. A widely accepted method to assess the drop reliability of microelectronics on board-level is the drop impact test. The drop impact test has been standardized by international councils like JEDEC and is widely adopted throughout the industry. The intention of the drop test is to assess the overall product reliability towards dropping, focusing on the solder interconnections. These solder interconnections are usually the first link in the chain to fail. Clearly the drop impact reliability of a product is also influenced by numerous design factors like material compositions, ball layout and product size as well as manufacturing conditions. Solder loading is investigated in this research by using high-speed camera recordings of several drop impact tests with verified Finite Element models. These simulation models are developed in order to gain an insight on the loading pattern of solder joints based on product specifications, interconnect layout and drop conditions prior to physical prototyping. Deflections and frequencies during drop testing are measured using a high-speed camera setup. The high-speed camera experiments are performed on two levels: product level (with different levels of energy and different pulse times) and machine level (rebounds with and without a catcher). Parametric (dynamic and quasi static) 3D models are developed to predict the drop impact performance. The experimental results are used to verify and enhance the simulation models, e.g. by tuning the damping parameters. As a result, the verified models can be used to determine the location of the critical solder joint and to obtain estimates of the solder lifetime performance.
Starting Page	1
Ending Page	6
File Size	1524186
Page Count	6
File Format	PDF
ISBN	9781424421275
DOI	10.1109/ESIME.2008.4525029
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-04-20
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Testing Cameras Home appliances Environmentally friendly manufacturing techniques Lead Microelectronics Chip scale packaging Integrated circuit packaging Wafer scale integration Soldering
Content Type	Text
Resource Type	Article

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