NDLI: Parametric analyses on fatigue reliability of 3D IC packages with built through silicon vias (TSVs)

Content Provider	IEEE Xplore Digital Library
Author	Chieh Kung Te-Tang Liao Chien-Hsiang Liao
Copyright Year	2012
Description	Author affiliation: Department of Electrical and Computer Engineering, National Chiao Tung University, Hsinchu City 30010, Taiwan, ROC (Chien-Hsiang Liao) \|\| Department of Mechanical, Engineering, Far East University, Xinshi, Tainan 74448, Taiwan, ROC (Te-Tang Liao) \|\| Department of Computer Application, Engineering, Far East University, Xinshi, Tainan 74448, Taiwan, ROC (Chieh Kung)
Abstract	3D IC technology, an advanced IC package architecture, has drawn much interest in semi-conduct manufacturing. A 3-D integrated circuit is a chip in which two or more layers of active electronic components are integrated both vertically and horizontally into a single circuit. For this kind of package through silicon vias (TSVs) provide high wiring density interconnection, thus improve electrical performance due to shorter interconnection from the chip to the substrate. However, TSV technology is still facing severe challenges as the physical design problems due to the existence of the copper vias remain resolved. Apart from thermal expansion mismatch, the problems are due in part to many factors including design parameters such as via radius, via aspect ratio, via pitch, chip thickness, and underfill thickness. Presented in this paper are parametric analyses of the effects of selected design parameters on fatigue reliability of lead-free solder joints in a 3D IC package subjected to temperature cycling. The parameters considered are chip thickness, TSV pitch, TSV radius, underfill thickness, and the coefficient of thermal expansion of underfill. The results show that there is a monotonic down trend of the fatigue life as the chip thickness increases. Also, while the fatigue life decreases with via pitch, the radius of via is the least dominant parameter for present package.
Starting Page	121
Ending Page	126
File Size	489287
Page Count	6
File Format	PDF
ISBN	9781467312752
e-ISBN	9781467312783
DOI	10.1109/ICMA.2012.6282818
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-08-05
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Fatigue Soldering Integrated circuit modeling Lead Finite element methods Through-silicon vias finite element method 3D IC package through silicon vias lead-free
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in