NDLI: An All-Digital Delay-Locked Loop for DDR SDRAM Controller Applications

Content Provider	IEEE Xplore Digital Library
Author	Ching-Che Chung Pao-Lung Chen Chen-Yi Lee
Copyright Year	2006
Description	Author affiliation: Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu (Ching-Che Chung; Pao-Lung Chen; Chen-Yi Lee)
Abstract	This paper presents an all-digital delay-locked loop (DLL) for DDR SDRAM controller applications. The presented all-digital, cell-based, DLL-based five-phase multi-phase clock generator can generate the required fixed timing delay (tSD) for DDR SDRAM controller to capture the output data (DQ) correctly. The proposed DLL-based multi-phase clock generator architecture can lock to the harmonic of input clock period and still get a correct multi-phase clock output. Hence the design challenges to build a high resolution delay line with minimum intrinsic delay can be reduced. Simulation results and chip measurement results show that the proposed DLL can generate desired tSD delay with error < 7.6%. The power consumption of the proposed DLL is 4.1mW (at DDR-200) and is 9.0mW (at DDR-400)
Starting Page	1
Ending Page	4
File Size	4398091
Page Count	4
File Format	PDF
ISBN	1424401798
DOI	10.1109/VDAT.2006.258159
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-04-26
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	DRAM chips Clocks Timing Delay lines Frequency Phase locked loops Jitter Circuit noise Phase noise Energy consumption
Content Type	Text
Resource Type	Article

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