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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Myounggon Kang Wookghee Hahn Il Han Park Hocheol Lee Juyoung Park Youngsun Song Changgyu Eun Sanghyun Ju Kihwan Choi Youngho Lim Jong-Ho Lee Byung-Gook Park Hyungcheol Shin |
| Copyright Year | 2010 |
| Description | Author affiliation: Flash Design Team, Memory Business, Samsung Electronics Co., Ltd., Korea (Wookghee Hahn; Il Han Park; Hocheol Lee; Juyoung Park; Youngsun Song; Changgyu Eun; Sanghyun Ju; Kihwan Choi; Youngho Lim) || Inter-university Semiconductor, Research Center (ISRC) and School of Electrical Engineering and Computer Science, Seoul National University, San 56-1, Sillim-dong, Gwanak-gu, 151-742, Republic of Korea (Myounggon Kang; Jong-Ho Lee; Byung-Gook Park; Hyungcheol Shin) |
| Abstract | In this work, a SPICE-friendly hot carrier injection (HCI) model for NAND flash memory has been proposed. By applying the HCI model to the 32 nm NAND product, the simulation based on HCI model showed good agreement with the measurement results. Based on the proposed model, a complex problem regarding the program disturbance in the scaled NAND flash memory array can be predicted through simple circuit simulations. Moreover, it is very useful in developing the ultra-short channel devices for high density multi-level cell (MLC) NAND flash technologies. |
| Starting Page | 1 |
| Ending Page | 4 |
| File Size | 958913 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781424499977 |
| e-ISBN | 9781424499984 |
| DOI | 10.1109/EDSSC.2010.5713695 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2010-12-15 |
| Publisher Place | China |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Computational modeling Logic gates Very large scale integration |
| Content Type | Text |
| Resource Type | Article |
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