NDLI: Interconnect Challenges for 3D Multi-cores: From 3D Network-on-Chip to Cache Interconnects

Content Provider	IEEE Xplore Digital Library
Author	Vivet, P. Bernard, C. Guthmuller, E. Miro-Panades, I. Thonnart, Y. Clermidy, F.
Copyright Year	2015
Description	Author affiliation: CEA-LETI, Grenoble, France (Vivet, P.; Bernard, C.; Guthmuller, E.; Miro-Panades, I.; Thonnart, Y.; Clermidy, F.)
Abstract	With the era of massive multi-core architecture targeting cloud computing for high end performances or advanced consumer electronics with tighter power consumption constraints, 3D integration technology will allow to design large scale multi-core. Thanks to advanced available 3D technology, it will be possible to maintain overall power consumption budget, increase chip to chip bandwidth, and preserve overall system cost by smart system partitioning. One of the main challenge of such multi-cores is clearly the interconnect infrastructure. For designing such 3D multi-cores, it is required to address two primary concerns: the 3D physical link by itself, and advanced interconnects scaled to 3D. The paper present an overview of 3Dinterconnects with 3D asynchronous Network-on-Chip architectures, with focus on 3D asynchronous links, and advanced interconnect structures for memory caches in 3D.
Starting Page	615
Ending Page	620
File Size	1692237
Page Count	6
File Format	PDF
e-ISBN	9781479987191
DOI	10.1109/ISVLSI.2015.21
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-07-08
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Three-dimensional displays Protocols Delays Through-silicon vias Stacking Throughput Integrated circuit interconnections Cache protocol 3D architecture TSV Network-on-Chip Asynchronous communication Serial Link
Content Type	Text
Resource Type	Article

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