NDLI: VLSI Implementation of an Improved Multiplier for FFT Computation in Biomedical Applications

Content Provider	IEEE Xplore Digital Library
Author	Ajay, A. Lourde, R.M.
Copyright Year	2015
Description	Author affiliation: Dept. of Electr. & Electron. Eng., BITS Pilani, Dubai, United Arab Emirates (Ajay, A.; Lourde, R.M.)
Abstract	Discrete Fourier Transform (DFT) is a fundamental Digital Signal Processing domain transformation technique used in many applications for frequency analysis and frequency domain processing. Fast Fourier Transform (FFT) is used for signal processing applications. It consists of addition and multiplication operations, whose speed improvement will enhance the accuracy and performance of FFT computation for any application. It is an algorithm to compute Discrete Fourier Transform (DFT) and its inverse. DFT is obtained by decomposing a sequence of values into components of different frequencies. FFT can compute DFT in O(N log N) operations unlike DFT computation that takes O(N2) arithmetic operations . This reduces computation time by several orders of magnitude and the improvement is roughly proportional to N / log N. Present day Research focus is on performance improvement in computation of FFT specific to field of application. Many performance improvement studies are in progress to implement efficient FFT computation through better performing multipliers and adders.Electroencephalographic (EEG) signals are invariably used for clinical diagnosis and conventional cognitive neuroscience. This work intends to contribute to a faster method of computation of FFT for analysis of EEG signals to classify Autistic data.
Starting Page	68
Ending Page	73
File Size	487648
Page Count	6
File Format	PDF
e-ISBN	9781479987191
DOI	10.1109/ISVLSI.2015.104
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-07-08
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Electroencephalography Discrete Fourier transforms Algorithm design and analysis Adders Hardware design languages Hardware Electrodes EEG FFT Multiplier
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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