NDLI: TSV capacitance aware 3-D floorplanning

Content Provider	IEEE Xplore Digital Library
Author	Ahmed, M.A. Chrzanowska-Jeske, M.
Copyright Year	2013
Abstract	3D-IC design facilitates reduction in wirelength by vertically stacking dies. Through-silicon-vias (TSVs) are used to connect inter-die signals. The dynamic power consumption of interconnects in 3D-IC is contributed by wires, buffers and TSVs. The delay in interconnects for 3D-IC is greatly influence by TSV capacitance. In this paper we propose TSV capacitance-aware 3D floorplanning to reduce the delay and dynamic power consumption in 3D-interconnects. The TSVs with specified dimensions and pitch are positioned in islands. TSV islands offer advantages over individual TSVs like reduced stress impact and more efficient inclusion of redundancy. TSV capacitance depends on TSV dimensions, pitch and wire technology. TSV capacitance aware floorplanning reduces power consumption in interconnects on average by 7% when using Cu-TSVs and 9% for W-TSVs. The approach also reduces peak delay for nets using Cu based TSVs on average by 15% and W based TSVs by 21%.
Sponsorship	IEEE Components, Pack., Manuf. Technol. Soc.
Starting Page	1
Ending Page	6
File Size	613725
Page Count	6
File Format	PDF
ISBN	9781467364843
DOI	10.1109/3DIC.2013.6702358
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-10-02
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Power demand Three-dimensional displays Interconnect Power Wires Integrated circuit interconnections 3D-IC Floorplanning Capacitance Delays Through-silicon vias Through-Silicon-Vias (TSVs)
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Delay and power optimization with TSV-aware 3D floorplanning

TSVs-aware floorplanning for 3D integrated circuit

Dynamic nets-to-TSVs assignment in 3D floorplanning

A novel circuit model for multiple Through Silicon Vias (TSVs) in 3D IC

On Through Silicon Vias as used in three dimensional integrated circuits

Enabling inter-die co-optimization in 3-D IC with TSVs

I/O power estimation and analysis of high-speed channels in through-silicon via (TSV)-based 3D IC

Structure optimization of through silicon via (TSV) interconnect as transmission channel for 3D integration

TSV-virtualization for Multi-protocol-Interconnect in 3D-ICs

TSV capacitance aware 3-D floorplanning

Similar Documents

Delay and power optimization with TSV-aware 3D floorplanning

TSVs-aware floorplanning for 3D integrated circuit

Dynamic nets-to-TSVs assignment in 3D floorplanning

A novel circuit model for multiple Through Silicon Vias (TSVs) in 3D IC

On Through Silicon Vias as used in three dimensional integrated circuits

Enabling inter-die co-optimization in 3-D IC with TSVs

I/O power estimation and analysis of high-speed channels in through-silicon via (TSV)-based 3D IC

Structure optimization of through silicon via (TSV) interconnect as transmission channel for 3D integration

TSV-virtualization for Multi-protocol-Interconnect in 3D-ICs

TSV capacitance aware 3-D floorplanning