NDLI: World's first monolithic 3D-FPGA with TFT SRAM over 90nm 9 layer Cu CMOS

Content Provider	IEEE Xplore Digital Library
Author	Naito, T. Ishida, T. Onoduka, T. Nishigoori, M. Nakayama, T. Ueno, Y. Ishimoto, Y. Suzuki, A. Chung, W. Madurawe, R. Wu, S. Ikeda, S. Oyamatsu, H.
Copyright Year	2010
Description	Author affiliation: Tier Logic Inc., 3500, Matsuoka, OitaCity, OitaPref., 870-0197, Japan (Madurawe, R.; Wu, S.) \|\| System LSI Division, Semiconductor Company, Toshiba Corporation, 3500, Matsuoka, OitaCity, OitaPref., 870-0197, Japan (Naito, T.; Ishida, T.; Nishigoori, M.; Nakayama, T.; Ueno, Y.; Ishimoto, Y.; Suzuki, A.; Chung, W.; Oyamatsu, H.) \|\| Tei Technology, 3500, Matsuoka, OitaCity, OitaPref., 870-0197, Japan (Ikeda, S.) \|\| Covalent Materials Corp., 3500, Matsuoka, OitaCity, OitaPref., 870-0197, Japan (Onoduka, T.)
Abstract	World's first monolithically integrated Thin-Film-Transistor (TFT) SRAM configuration circuits over 90nm 9 layers of Cu interconnect CMOS is successfully fabricated at 300mm LSI mass production line for 3-dimensional Field Programmable Gate Arrays (3D-FPGA). This novel technology built over the $9^{th}$ layer of Cu metal features aggressively scaled amorphous Si TFT having 180nm transistor gate length, 20nm gate oxide, fully silicided gate, S/D, all below 400C processing essential to not impact underlying Cu interconnects. Low temperature TFT devices show excellent NTFT/PTFT transistor I ratios over 2000/100 respectively, operate at 3.3V, E-field scalable, and are stable for SRAM configuration circuits. We believe this 3D-TFT technology is a major breakthrough innovation to overcome the conventional CMOS device shrinking limitation.
Starting Page	219
Ending Page	220
File Size	596837
Page Count	2
File Format	PDF
ISBN	9781424454518
e-ISBN	9781424454501
DOI	10.1109/VLSIT.2010.5556234
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-06-15
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Thin film transistors Logic gates CMOS integrated circuits Random access memory Copper CMOS technology
Content Type	Text
Resource Type	Article

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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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