NDLI: Suppression of anomalous threshold voltage increase with area scaling for Mg- or La-incorporated high-k/Metal gate nMISFETs in deeply scaled region

Content Provider	IEEE Xplore Digital Library
Author	Morooka, T. Sato, M. Matsuki, T. Suzuki, T. Shiraishi, K. Uedono, A. Miyazaki, S. Ohmori, K. Yamada, K. Nabatame, T. Chikyow, T. Yugami, J. Ikeda, K. Ohji, Y.
Copyright Year	2010
Description	Author affiliation: Semiconductor Leading Edge Technologies, Inc. , 16-1 Onogawa, Tsukuba, Ibaraki, 305-8569, Japan (Morooka, T.; Sato, M.; Matsuki, T.; Suzuki, T.; Yugami, J.; Ikeda, K.; Ohji, Y.) \|\| National Institute for Materials Science, Japan (Nabatame, T.; Chikyow, T.) \|\| Waseda University, Japan (Ohmori, K.; Yamada, K.) \|\| Hiroshima University, Japan (Miyazaki, S.) \|\| Tsukuba University, Japan (Shiraishi, K.; Uedono, A.)
Abstract	Anomalous threshold voltage increase with area scaling of Mg- or La-incorporated high-k gate dielectrics has great impact on scaled devices. This paper reveals that much amount of Mg or La capping effects for V reduction was disappeared with the increase of electron mobility in narrow channel nMISFETs. This phenomenon is explained with absorption of Mg and La into STI from bulk high-k layer. The key to suppress the area scaling dependence is pilling Mg or La atoms up near high-k/IFL interface which enable us increase of stable capping effect. Combination of processing for high-k gate dielectrics and device structure with the high-k dielectrics under offset spacers was found to effectively suppress the V increase at the 100 nm channel width. As a conclusion, the large capping effect for V reduction over 400 mV is achieved in scaled devices using this technique.
Starting Page	33
Ending Page	34
File Size	439192
Page Count	2
File Format	PDF
ISBN	9781424454518
e-ISBN	9781424454501
DOI	10.1109/VLSIT.2010.5556129
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-06-15
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	High K dielectric materials Logic gates Tin Silicon Atomic layer deposition Capacitors
Content Type	Text
Resource Type	Article

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