NDLI: Low power 6T-SRAM

Content Provider	IEEE Xplore Digital Library
Author	Saurabh Srivastava, P.
Copyright Year	2012
Description	Author affiliation: Electron. & Commun. Eng., LNM Inst. of Inf. Technol., Jaipur, India (Saurabh) \|\| Dept. of Phys., Indian Inst. of Inf. Technol. & Manegement, Gwalior, India (Srivastava, P.)
Abstract	This paper focuses on minimizing the Power consumption during Write and Standby operations and delay during Write in a 6T-SRAM cell by using a new Proposed architectural design in 32 nm technology and comparing the results with the architectural designs being used nowadays. As microprocessors and other electronics applications get faster and faster, the need for large quantities of data at very high speeds increases. Static Random Access Memory (SRAM) is an important memory device which stores data on a chip. SRAM acts as a Cache memory - providing a direct interface with the CPU at a speed which can never be attained by DRAMs. The Proposed 6-T architecture of SRAM cell is designed and implemented using 32 nm CMOS technology and results have been compared with the existing architectures which are widely in use. The results shows approx. 7.7% and 26% improvement in Power consumption during `Write operation' and `Standby condition' respectively and significant decrease in `Write delay' apart from 31% improvement in terms of `Area' of the chip used. The Proposed architecture has been designed and simulated by Microwind 3.1 software.
Starting Page	1
Ending Page	4
File Size	2137456
Page Count	4
File Format	PDF
e-ISBN	9781467331364
DOI	10.1109/ICEmElec.2012.6636251
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-12-15
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Cache memory Random access memory Logic gates CMOS technology Inverters CMOS integrated circuits Low power Delay
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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