NDLI: Short-channel performance and mobility analysis of <110>- and <100>-oriented tri-gate nanowire MOSFETs with raised source/drain extensions

Content Provider	IEEE Xplore Digital Library
Author	Saitoh, M. Nakabayashi, Y. Itokawa, H. Murano, M. Mizushima, I. Uchida, K. Numata, T.
Copyright Year	2010
Description	Author affiliation: Advanced LSI Technology Laboratory, Corporate R&D Center, 8 Shinsugita-cho, Isogo-ku, Yokohama 235-8522, Japan (Saitoh, M.; Nakabayashi, Y.; Numata, T.) \|\| Tokyo Institute of Technology, 8 Shinsugita-cho, Isogo-ku, Yokohama 235-8522, Japan (Uchida, K.) \|\| Process & Manufacturing Engineering Center, Semiconductor Company, Toshiba Corporation, 8 Shinsugita-cho, Isogo-ku, Yokohama 235-8522, Japan (Itokawa, H.; Murano, M.; Mizushima, I.)
Abstract	We successfully reduced the parasitic resistance of nanowire transistors (NW Tr.) by raised S/D extensions with thin spacers (<10nm). I variations are suppressed by spacer thinning and parasitic capacitance increase is minimal. By adopting <100> NW instead of <110> NW, I = 1mA/µm for I = 100nA/µm is achieved without stress techniques. Long-L mobility (μ) was systematically studied by separating top and side channel μ. μ of <100> nFETs and <110> pFETs (potentially-high μ) largely degrade due to side-surface roughness. Gate stress and interface traps affect μ of <110> nFETs and <110> pFETs, respectively.
Starting Page	169
Ending Page	170
File Size	458314
Page Count	2
File Format	PDF
ISBN	9781424454518
e-ISBN	9781424454501
DOI	10.1109/VLSIT.2010.5556214
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-06-15
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Logic gates Stress Degradation Strain Silicon Silicon compounds Rough surfaces
Content Type	Text
Resource Type	Article

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