NDLI: Embedded SiGe source/drain and temperature degrading junction performance on <110> 45 nm MOSFETs

Content Provider	IEEE Xplore Digital Library
Author	Mu-Chun Wang Long-Sian Lin Heng-Sheng Huang Wen-Shiang Liao Ren-Hau Yang Hsin-Chia Yang
Copyright Year	2011
Description	Author affiliation: Dept. of Electronic Engineering, Minghsin University of Science and Technology, Hsinchu, Taiwan (Wen-Shiang Liao; Ren-Hau Yang; Hsin-Chia Yang) \|\| Graduate Institute of Mechatronic Engineering, National Taipei University of Technology, Taipei, Taiwan (Mu-Chun Wang; Long-Sian Lin; Heng-Sheng Huang)
Abstract	Embedded SiGe process technology in source/drain is an available method to do the compressive strain in PMOSFETs to increase the channel mobility. However, the fringe junction leakage close to gate electrodes, comparing that with the control group, is increased more. When the temperature effect is incorporated, this deterioration is more obvious. Through the decouple technology with feasible junction pattern design, the fringe junction leakage issue can be effectively extracted and clarified.
Starting Page	1
Ending Page	2
File Size	364575
Page Count	2
File Format	PDF
ISBN	9781457703799
ISSN	21593531
e-ISBN	9781457703782
e-ISBN	9781457703775
DOI	10.1109/INEC.2011.5991638
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-06-21
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	strain MOSFET Embedded SiGe Logic gates Silicon junction leakage IP networks Junctions MOSFETs Silicon germanium Strain
Content Type	Text
Resource Type	Article

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