NDLI: R-1: Navigating the Roadmap to 32nm and Beyond: Breaking the Barriers

Content Provider	IEEE Xplore Digital Library
Author	Inaba, S. Arghavani, R. Patton, G. Liang, M. Toyoshima, Y. Nishi, Y. Chau, R. Skotnicki, T.
Copyright Year	2007
Description	Author affiliation: Toshiba Corp., Tokyo (Inaba, S.)
Abstract	The transition to sub-90 nm node shifted a paradigm in logic LSI. Traditional device scaling methods failed to boost sufficient performance to uphold Moore's Law. The 90 nm node, therefore, debuted with uniaxial strain engineering to improve device performance. The final scaled gate oxynitride dielectric (<5 atomic layers thick) was also introduced. The 65 nm node continued this scaling path with more enhanced stress inducing films in the front end. Gate dielectric was only slightly scaled at this node. Initial 45 nm node announcements indicate the introduction of immersion lithography, multiple strain inducing films, which use the additivity aspect of various strain inducing films, and PVD hard masks which enhance CD control. The introduction of high-k gate dielectric and metal gate at 45 nm node is hailed as the "'biggest change to computer chips in 40 years". Extrapolation of existing device trends shows significant barriers to the 32 nm technology node. Uniaxial process-induced strain engineering methods, based on new families of ultra-high stress inducing films combined with embedded SiGe or embedded SiC structure at the source/drain, hold promise for achieving 32 nm node device targets. Other process area advances may assist in hitting this mark such as: low resistivity contacts, dual silicides, low-k spacers, single wafer cleans to reduce defect density and eCMP methods with chemistries to reduce variability in lithography and etch. This panel discussion addresses various technologies and lead 32 nm enabling options for further improving CMOS performance. Which sub 32 nm transistor structures are most viable for logic and SRAM applications? What does the future hold for High-k and Metal gate? What are the emerging challenges in device parasitics? What material selection guidelines will keep compatibility between generations? How to control the device characteristic variability? The distinguished panelists will also debate the viability of the above techniques to extend Moore's Law toward 32 nm node and beyond.
Starting Page	151
Ending Page	151
File Size	619803
Page Count	1
File Format	PDF
ISBN	9784900784031
DOI	10.1109/VLSIT.2007.4339772
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-06-12
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	JSAP
Subject Keyword	Navigation Logic devices Moore's Law Uniaxial strain Dielectrics Stress Lithography Capacitive sensors Large scale integration Atomic layer deposition
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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