NDLI: Advanced electrical characterization toward (sub) 1nm EOT HfSiON - hole trapping in PFET and L-dependent effects

Content Provider	IEEE Xplore Digital Library
Author	Zahid, M.B. Pantisano, L. Degraeve, R. Aoulaiche, M. Trojman, L. Ferain, I. San Andres, E. Groeseneken, G. Zhang, J.F. Heyns, M. Jurczak, M. De Gendt, S.
Copyright Year	2007
Description	Author affiliation: IMEC (Interuniv. Microelectron. Centre), Leuven (Zahid, M.B.; Pantisano, L.; Degraeve, R.; Aoulaiche, M.; Trojman, L.; Ferain, I.)
Abstract	Hf-based gate dielectrics layers with EOT≪1nm are actively investigated for 22nm node and beyond. EOT scalability of these films is simultaneously achieved by reducing the high-k thickness as well as optimizing the N-profile into the thin film. For Hf-based layers electron traps in the upper part of the bandgap have been a major concern for nMOSFETs since they cause $V_{T}-instability$ and affect mobility [1]. With the scaling of EOT to 1 nm and below, the impact of these traps has, however, disappeared [2]. Electron traps have never been considered a potential problem for PMOS because at negative bias they are always efficiently discharged. We found, however, that in PMOS with EOT ˜1 nm, a large hysteresis at high field is observed in the $I_{D}-V_{G}$ characteristics, while no hysteresis is measured on the corresponding NMOS devices (on the same wafer) (Fig. 1). In this work we will prove by an advanced charge pumping technique that the hysteresis in PMOS is caused by hole traps in the high-k layer. Furthermore, we show how NBTI defects are correlated with such hole traps. Hole trap density depends on the Hf- and N-profile in the film, being larger for Hf-rich films.
Starting Page	32
Ending Page	33
File Size	474589
Page Count	2
File Format	PDF
ISBN	9784900784031
DOI	10.1109/VLSIT.2007.4339715
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-06-12
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	JSAP
Subject Keyword	Electron traps Dielectric thin films Hysteresis High K dielectric materials High-K gate dielectrics Scalability Photonic band gap MOSFETs MOS devices Charge pumps
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Energy distribution of interface traps in high-k gated MOSFETs

High mobility high-k/Ge pMOSFETs with 1 nm EOT -New concept on interface engineering and interface characterization

Charge trapping dependence on the physical structure of ultra-thin ALD-HfSiON/TiN gate stacks

Study of charge trapping/detrapping mechanism in SiO2/HfO2 stack gate dielectrics considering two-way detrapping

Leakage effect suppression in charge pumping measurement and stress-induced traps in high-k Gated MOSFETs

Germanium for advanced CMOS anno 2009: a SWOT analysis

A critical review of charge-trapping NAND flash devices

Inversion n-channel GaN MOSFETs with atomic-layer-deposited A12O3 as gate dielectrics

Charge trapping by oxygen-related defects in HfO/sub 2/-based high-k gate dielectrics [MOSFETs]

Advanced electrical characterization toward (sub) 1nm EOT HfSiON - hole trapping in PFET and L-dependent effects

Similar Documents

Energy distribution of interface traps in high-k gated MOSFETs

High mobility high-k/Ge pMOSFETs with 1 nm EOT -New concept on interface engineering and interface characterization

Charge trapping dependence on the physical structure of ultra-thin ALD-HfSiON/TiN gate stacks

Study of charge trapping/detrapping mechanism in SiO2/HfO2 stack gate dielectrics considering two-way detrapping

Leakage effect suppression in charge pumping measurement and stress-induced traps in high-k Gated MOSFETs

Germanium for advanced CMOS anno 2009: a SWOT analysis

A critical review of charge-trapping NAND flash devices

Inversion n-channel GaN MOSFETs with atomic-layer-deposited A12O3 as gate dielectrics

Charge trapping by oxygen-related defects in HfO/sub 2/-based high-k gate dielectrics [MOSFETs]

Advanced electrical characterization toward (sub) 1nm EOT HfSiON - hole trapping in PFET and L-dependent effects