NDLI: Strain enhanced FUSI/HfSiON Technology with optimized CMOS Process Window

Content Provider	IEEE Xplore Digital Library
Author	Veioso, A. Verheyen, P. Vos, R. Brus, S. Ito, S. Mitsuhashi, R. Paraschiv, V. Shi, X. Onsia, B. Arnauts, S. Loo, R. Lauwers, A. Conard, T. de Marneffe, J.-F. Goossens, D. Baute, D. Locorotondo, S. Chiarella, T. Kerner, C. Vrancken, C. Mertens, S. O'Sullivan, B.J. Yu, H.Y. Chang, S.-Z. Niwa, M. Kittl, J.A. Absil, P.P. Jurczak, M. Hoffmann, T. Biesemans, S.
Copyright Year	2007
Description	Author affiliation: IMEC, Leuven (Veioso, A.; Verheyen, P.; Vos, R.; Brus, S.)
Abstract	We report, for the first time, a comprehensive study on the compatibility of state-of-the-art performance boosters with FUSI/HfSiON technology, resulting in record $high-V_{T}$ NMOS and PMOS devices with 725/370 muA/mum (at $V_{DD}=1.1$ V, $I_{off}=20$ pA/mum and $J_{g}=$ 100/1 $mA/cm^{2}).$ We demonstrate that adding embedded $Si_{0.75}Ge_{0.25}$ in S/D regions resulted in 45% performance improvement over the FUSI/HfSiON reference, and that the $V_{T}$ distribution is tight and comparable to baseline. For process simplicity purposes, dual phase Ni-FUSI (NiSi NMOS; $Ni_{31}Si_{12}$ or $Ni_{2}Si$ PMOS) is formed simultaneously in our integration scheme, each phase having its own process window (PW). In this work, we successfully maximized the common CMOS PW by 2 crucial process improvements: -shifting up the NMOS RTP1 temperature (T) PW by nitrogen implantation in NMOS poly gates prior to Ni deposition for FUSI; -extending the PMOS PW to lower RTP1 temperatures by improved surface preparation after novel poly etch-back process.
Starting Page	200
Ending Page	201
File Size	997277
Page Count	2
File Format	PDF
ISBN	9784900784031
DOI	10.1109/VLSIT.2007.4339692
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-06-12
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	JSAP
Subject Keyword	Capacitive sensors CMOS technology CMOS process MOS devices Silicon germanium Germanium silicon alloys Etching Tensile stress Surface-mount technology Temperature
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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