NDLI: High-level synthesis with variable-latency components

Content Provider	IEEE Xplore Digital Library
Author	Raghunathan, V. Ravi, S. Lakshminarayana, G.
Copyright Year	2000
Description	Author affiliation: Dept. of Electr. Eng., Indian Inst. of Technol., Bombay, India (Raghunathan, V.)
Abstract	This paper presents techniques to integrate the use of variable latency units in a high-level synthesis design methodology. Components used as building blocks (e.g., functional units) in conventional high-level synthesis techniques are assumed to have fixed latency values. Variable latency units exhibit the property that the number of cycles taken to compute their outputs varies depending on the input values. While variable latency units offer potential for performance improvement, we demonstrate that realization of this potential requires that high-level synthesis be adapted suitably (sub-optimal use of variable latency units can lead to performance degradation, or unnecessarily high area overheads). Our techniques to incorporate variable latency units into high-level synthesis ensure that the performance improvement is maximized, while minimizing area overheads or satisfying resource constraints. These techniques do not assume specific high-level synthesis tools/algorithms, and can be plugged in to any generic high-level synthesis system. Since area overheads may still be incurred due to the use of variable latency units, we present a novel technique, based on the concept of reduced variable latency units, to further reduce area overheads. Reduced variable latency-units only implement the low latency case behavior of complete variable latency units. The use of reduced variable latency units significantly reduces area overheads, and frequently results in RTL implementations with simultaneous area and performance improvements compared to fixed latency implementations. Experimental results show that designs optimized using the proposed techniques achieve significant performance improvements (upto 1.6 X) over designs synthesized by a state-of-the-art high level synthesis tool, frequently with simultaneous improvements in area (upto 17.9%). In addition, while we do not explicitly target power reduction, we found the variable latency optimized designs to consume 35.7% less power on the average.
Starting Page	220
Ending Page	227
File Size	160579
Page Count	8
File Format	PDF
ISBN	0769504876
ISSN	10639667
DOI	10.1109/ICVD.2000.812612
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2000-01-03
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	High level synthesis Delay Circuits Adders Statistics Design optimization Clocks Automatic control National electric code Design methodology
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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