NDLI: Cost trade-offs in system on chip designs

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Cost trade-offs in system on chip designs

Content Provider	IEEE Xplore Digital Library
Author	Khare, J. Heineken, H.T. d'Abreu, M.
Copyright Year	2000
Description	Author affiliation: DFM/DFT Group, Level One Commun., Sacrameto, CA, USA (Khare, J.)
Abstract	Advances in technology have led to a drive towards system on chip (SoC) designs. However manufacturing and test costs have increased as rapidly as design complexity. Hence, in order to produce SoC designs at reasonable cost, both system-level and die-level cost trade-offs must be made. This paper illustrates the methodologies used in analyzing such trade-offs. Examples in the paper indicate that using advanced technologies to manufacture SoC designs may sometimes be detrimental in terms of total system costs.
Starting Page	178
Ending Page	184
File Size	68013
Page Count	7
File Format	PDF
ISBN	0769504876
ISSN	10639667
DOI	10.1109/ICVD.2000.812606
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2000-01-03
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Costs System-on-a-chip Manufacturing Radio frequency Random access memory Packaging Graphics Logic Design for manufacture Design for testability
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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