NDLI: Study on FPGA SEU mitigation for readout electronics of DAMPE BGO calorimeter

Content Provider	IEEE Xplore Digital Library
Author	Zhongtao Shen Changqing Feng Shanshan Gao Deliang Zhang Di Jiang Shubin Liu Qi An
Copyright Year	2014
Description	Author affiliation: State Key Lab. of Particle Detection & Electron., Univ. of Sci. & Technol. of China, Hefei, China (Zhongtao Shen; Changqing Feng; Shanshan Gao; Deliang Zhang; Di Jiang; Shubin Liu; Qi An)
Abstract	The Dark Matter Particle Explorer (DAMPE) is being constructed as a scientific satellite to observe high energy cosmic rays in space. As a main detector of DAMPE, the Bismuth Germanium Oxide (BGO) calorimeter is in charge of measuring particle energy deposition, distinguishing positrons, electrons and gamma rays from hadron background and providing trigger information. The satellite is designed to fly on a near-earth orbit with an altitude of 500km, which makes demands on electronic components for the ability to work in radiation environment.A flash-based Field-Programmable Gate Array (FPGA) of Actel, ProASCI Plus (APA) is chosen as the control component of the Front-End Electronics (FEE). To study the radiation resistance, SEE test was performed at the Heavy Ion Research Facility in Lanzhou (HIRFL). The chip did not exhibit latchup to an effective LET of 90 MeV-cm2/mg. The Flash switches of APA, which provide nonvolatile, reconfigurable interconnect programming and connect routing nets, were immune to SEL. However, SEE experiment also showed that the registers implemented from logic tiles and RAM blocks were SEU sensitive. Therefore, appropriate solutions should be adopted to mitigate SEU effects and make sure that the chip can function well in the radiation environment of space. To achieve maximum SEU tolerance with minimum resource consumption and speed degradation, engineering tradeoffs should be taken into account. Firstly, to the crucial registers and RAMs, Triple Modular Redundancy (TMR) technique is used to ensure that the value after voter is correct and if the values in three modules are different, the voter result will be written back to modules to scrub SEU errors. Besides, the three modules are manually placed in different physical areas to avoid Multiple Bit Upset (MBU). Secondly, CRC checksum is used to check the correctness of configuration data stored in RAM, which can be used as judgment of RAM reconfiguration. And thirdly, the whole logic is divided into four parts with different reset signals, which makes it convenient to set the idle parts into sleep until the external wake-up signals come. After using these means in the logic design, an ion-beam testing is performed to evaluate the SEU tolerance of FPGA logic. The FPGA works well under the condition with the LET of 39.6 MeV-cm2/mg and the ion flux of 100 ions/cm2/s without any mistake. The radiation test verifies that the SEU mitigationstrategies implemented in APA FPGA can meet the space qualification.
Starting Page	1
Ending Page	1
File Size	154110
Page Count	1
File Format	PDF
e-ISBN	9781479936595
DOI	10.1109/RTC.2014.7097551
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-05-26
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays Random access memory Aerospace electronics Single event upsets Satellites Space vehicles Registers SEU FPGA Mitigation
Content Type	Text
Resource Type	Article

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