NDLI: A highly parallel FPGA implementation of a 2D-clustering algorithm for the ATLAS Fast TracKer (FTK) processor

Content Provider	IEEE Xplore Digital Library
Author	Kimura, N. Annovi, A. Beretta, M. Gatta, M. Gkaitatzis, S. Iizawa, T. Kordas, K. Korikawa, T. Nikolaidis, S. Petridou, C. Sotiropoulou, C.-L. Yorita, K. Volpi, G.
Copyright Year	2014
Description	Author affiliation: Dept. of Phys., Aristotle Univ. of Thessaloniki, Thessaloniki, Greece (Gkaitatzis, S.; Kordas, K.; Nikolaidis, S.; Petridou, C.; Sotiropoulou, C.-L.) \|\| Lab. Naz. di Frascati, INFN, Frascati, Italy (Annovi, A.; Beretta, M.; Gatta, M.; Volpi, G.) \|\| Dept. of Physis, Waseda Univ., Tokyo, Japan (Kimura, N.; Iizawa, T.; Korikawa, T.; Yorita, K.)
Abstract	The highly parallel 2D-clustering FPGA implementation used for the input system of the Fast TracKer (FTK) processor for the ATLAS experiment of the Large Hadron Collider (LHC) at CERN is presented. The LHC after the 2013-2014 shutdown periods is planned to have increased luminosity, which will make it more difficult to have efficient online selection of rare events due to the increase of the overlapping collisions. FTK is a highly-parallelized hardware system that improves the online selection by executing real time track finding using the information from the silicon inner detector. The FTK system requires fast and robust clustering of the hits retrieved from the silicon detector on FPGA devices. We show the development of the original input boards and the implemented clustering algorithm. For the complicated 2D-clustering, a moving window technique is used to minimize the use of FPGA resources. The combination of custom developed boards and implementation of the clustering algorithm provides sufficient processing power to meet the specifications for the silicon inner detector of ATLAS up to the maximum LHC luminosity planned until 2022. The developed algorithm is easily adjustable to other image processing applications that require real-time 2D-clustering.
Starting Page	1
Ending Page	4
File Size	770564
Page Count	4
File Format	PDF
e-ISBN	9781479936595
DOI	10.1109/RTC.2014.7097431
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-05-26
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Detectors Field programmable gate arrays Clustering algorithms Large Hadron Collider Decoding Silicon Buffer storage
Content Type	Text
Resource Type	Article

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