NDLI: Evaluation of SRAM based FPGA performance by simulating SEU through fault injection

Content Provider	IEEE Xplore Digital Library
Author	Ibrahim, M.M. Asami, K. Mengu Cho
Copyright Year	2013
Description	Author affiliation: Integrated Syst. Eng. Dept., Kyushu Inst. of Technol., Kitakyushu, Japan (Ibrahim, M.M.; Asami, K.; Mengu Cho)
Abstract	This paper presents the technique and results of Single Event Upsets fault injection in the configuration bit-stream of SRAM-based FPGAs through partial reconfiguration of configuration frames. The Xilinx Virtex5 LX50 is used in the experiments. The Single Event Upset controller macro is used injecting faults to random locations of the FPGA bit-stream. The effects were studied on a design consisting of 4 embedded processor systems implemented in the FPGA. MATLAB is used for developing the external fault injection control environment.
Sponsorship	IEEE Aerosp. Electron. Syst. Soc.
Starting Page	649
Ending Page	654
File Size	679100
Page Count	6
File Format	PDF
ISBN	9781467363952
e-ISBN	9781467363969
DOI	10.1109/RAST.2013.6581290
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-06-12
Publisher Place	Turkey
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Space vehicles Redundancy FPGA Single event upsets Random access memory Orbits Table lookup Embedded Systems Single Event Upset Field programmable gate arrays Fault Injection Fault Tolerance
Content Type	Text
Resource Type	Article

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Evaluation of SRAM based FPGA performance by simulating SEU through fault injection