NDLI: IEEE 1588 time synchronization board in MTCA.4 form factor

Content Provider	IEEE Xplore Digital Library
Author	Jablonski, G. Makowski, D. Mielczarek, A. Orlikowski, M. Perek, P. Napieralski, A. Makijarvi, P. Simrock, S.
Copyright Year	2014
Description	Author affiliation: ITER Organ., St. Paul-lez-Durance, France (Makijarvi, P.; Simrock, S.) \|\| Dept. of Microelectron. & Comput. Sci., Lodz Univ. of Technol., Lodz, Poland (Jablonski, G.; Makowski, D.; Mielczarek, A.; Orlikowski, M.; Perek, P.; Napieralski, A.)
Abstract	The distributed data acquisition and control systems in large-scale scientific experiments, like e.g. ITER, require time synchronization with nanosecond precision. A protocol commonly used for that purpose is the Precise Timing Protocol (PTP), also known as IEEE 1588 standard. It uses the standard Ethernet signalling and protocols and allows obtaining timing accuracy of order of tens of nanoseconds. The MTCA.4 is gradually becoming the platform of choice for building such systems. Currently there is no commercially available implementation of PTP receiver on that platform. In the paper, we present the module in the MTCA.4 form factor supporting this standard. The module may be used as a timing receiver providing reference clocks in the MTCA.4 chassis, generating the Pulse Per Second (PPS) signal and allowing generation of triggers and timestamping of events on 8 configurable backplane lines and two front panel connectors. The module is based on the Xilinx Spartan 6 FPGA and thermally stabilized Voltage Controlled Oscillator controlled by the digital-to-analog converter. The board supports standalone operation, without the support from the host operating system, as the entire control algorithm is run on the Microblaze CPU implemented in FPGA. The software support for the card includes the low-level API in the form of the Linux driver and user-mode library and high-level API: ITER Nominal Device Support and EPICS IOC. The device has been tested in ITER timing distribution network (TCN) with three cascaded PTP-enabled Hirschmann switches and GPS reference clock source. An RMS synchronization accuracy measured by direct comparison of the PPS signals better than 20 ns has been obtained.
Starting Page	1
Ending Page	2
File Size	402357
Page Count	2
File Format	PDF
e-ISBN	9781479936595
DOI	10.1109/RTC.2014.7097411
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-05-26
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Clocks Synchronization Protocols Field programmable gate arrays Computer architecture Tokamaks Micro Telecommunications Computing Architecture IEEE 1588 PTP Field Programmable Gate Array
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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