NDLI: Validation of channel decoding ASIPs a case study

Content Provider	IEEE Xplore Digital Library
Author	Brehm, C. Wehn, N. Loitz, S. Kunz, W.
Copyright Year	2011
Description	Author affiliation: Microelectronic Systems Design Research Group, University of Kaiserslautern, Germany (Brehm, C.; Wehn, N.) \|\| Electronic Design Automation Research Group, University of Kaiserslautern, Germany (Loitz, S.; Kunz, W.)
Abstract	It is well known that validation and verification is the most time consuming step in complex System-on-Chip design. Thus, different validation and verification approaches and methodologies for various implementation styles have been devised and adopted by the industry. Application specific instruction set-processors (ASIPs) are an emerging implementation technology to solve the energy efficiency/flexibility trade-off in baseband processing for wireless communication where multiple standards have to be supported at a very low power budget and a small silicon footprint. In order to balance these contrary aims ASIPs for these application domains have a restricted functionality tailored to a specific class of algorithms compared to traditional ASIPs. Downside of the outstanding efficiency/flexibility ratio is the coincidence of bad attributes for validation. Compared to standard processors, these ASIPs often have a very complex instruction set architecture (ISA) due to the tight coupling between the instructions and the optimized micro-architecture requiring new validation concepts. This paper will sensitize for the distinctiveness and complexity of the validation of ASIPs tailored to channel decoding. In a case study a composite approach comprising formal methods as well as simulations and rapid-prototyping for validating an existing channel decoding ASIP is applied and transferred it into an industry product.
Starting Page	74
Ending Page	78
File Size	518377
Page Count	5
File Format	PDF
ISBN	9781457706585
e-ISBN	9781457706608
e-ISBN	9781457706592
DOI	10.1109/RSP.2011.5929978
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-05-24
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Computer architecture Decoding Pipelines Program processors Standards Hardware
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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