NDLI: A 50 MHz–6 GHz, 2 × 2 MIMO, reconfigurable architecture, software-defined radio in 130nm CMOS

Content Provider	IEEE Xplore Digital Library
Author	Analui, B. Mercer, T. Mandegaran, S. Goel, A. Hashemi, H.
Copyright Year	2014
Abstract	A monolithic 50 MHz-6 GHz software-defined radio transceiver with two transmit (TX) and two receive (RX) channels to support 2 × 2 MIMO is implemented in 130nm CMOS. The transmitter's and receiver's frequency translation modes are reconfigurable to direct conversion or dual up-down conversion, featuring an on chip Q-enhanced 3 GHz 6-pole Chebyshev IF BPF in the dual conversion mode. The chip also includes two independent integrated wide-band frequency synthesizers for TX and RX paths to support Frequency Division Duplex (FDD) radios. Each frequency synthesizer has an integrated 50 MHz Direct Digital Synthesis (DDS) based reference into an integer-N PLL with integrated 3-tank VCOs, integrated loop-filter, and a zero-spur phase-frequency detector, to achieve low-spur and high resolution, simultaneously. The radio has >0 dBm $TXP_{-1dB}$ and >70 dB RX blocker tolerance (in-band and out of band) with <; 900 mW worst case total power consumption per transceiver channel.
Starting Page	329
Ending Page	332
File Size	1409724
Page Count	4
File Format	PDF
ISBN	9781479938629
ISSN	15292517
e-ISBN	9781479938643
DOI	10.1109/RFIC.2014.6851733
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-06-01
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Frequency synthesizers Transceivers Receivers Radio transmitters Frequency conversion Noise Current measurement Wideband CMOS MIMO Reconfigurable SDR Transceiver
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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