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Content Provider | IEEE Xplore Digital Library |
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Author | Hezar, R. Lei Ding Joonhoi Hur Haroun, B. |
Copyright Year | 2014 |
Description | Author affiliation: Texas Instrum., Dallas, TX, USA (Hezar, R.; Lei Ding; Joonhoi Hur; Haroun, B.) |
Abstract | This paper presents a 23 dBm fully digital transmitter designed in a standard 45 nm CMOS process. The digital transmitter replaces the entire analog/RF signal chain in a traditional transmitter architecture. It utilizes ΣΔ modulation and pulse-width modulation to turn high resolution baseband I and Q signals into switching signals, thereby allowing efficient Class-D PA stages to be used. In addition, cascaded ΣΔ stages and switched-capacitor combining are incorporated into the architecture to reduced out-of-band quantization noise while maintaining good efficiency. The proposed transmitter achieves peak output power of 23 dBm with 47% power added efficiency (PAE). For a OFDM signal with 8.2 dB peak-to-average power ratio (PAR), the PAE is 23%. The linearity of the digital transmitter meets WiFi spectral mask without any digital predistortion. |
Starting Page | 217 |
Ending Page | 220 |
File Size | 945902 |
Page Count | 4 |
File Format | |
ISBN | 9781479938629 |
ISSN | 15292517 |
e-ISBN | 9781479938643 |
DOI | 10.1109/RFIC.2014.6851702 |
Language | English |
Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Publisher Date | 2014-06-01 |
Publisher Place | USA |
Access Restriction | Subscribed |
Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subject Keyword | Radio frequency Transmitters CMOS integrated circuits Pulse width modulation Switches Peak to average power ratio switched-capacitor power amplifier sigma-delta modulation pulse-width modulation Class-D CMOS power amplifier |
Content Type | Text |
Resource Type | Article |
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