NDLI: A 2×2 MIMO 802.11 abgn/ac WLAN SoC with integrated T/R switch and on-chip PA delivering VHT80 256QAM 17.5dBm in 55nm CMOS

Content Provider	IEEE Xplore Digital Library
Author	Tsung-Ming Chen Wei-Chia Chan Chien-Cheng Lin Jui-Lin Hsu Wen-Kai Li Pi-An Wu Yen-Lin Huang Yen-Chuan Huang TzungChuen Tsai Po-Yu Chang Chih-Lung Chen Chih-Hou Tsai Tao-Yao Chang I-Ching Huang Wen-Hsien Chiu Chun-Hao Liao Chia-Hsin Wu Chien, G.
Copyright Year	2014
Description	Author affiliation: MediaTek Inc., Hsinchu, Taiwan (Tsung-Ming Chen; Wei-Chia Chan; Chien-Cheng Lin; Jui-Lin Hsu; Wen-Kai Li; Pi-An Wu; Yen-Lin Huang; Yen-Chuan Huang; TzungChuen Tsai; Po-Yu Chang; Chih-Lung Chen; Chih-Hou Tsai; Tao-Yao Chang; I-Ching Huang; Wen-Hsien Chiu; Chun-Hao Liao; Chia-Hsin Wu) \|\| MediaTek Inc., San Jose, CA, USA (Chien, G.)
Abstract	This paper describes 2×2 MIMO 802.11ac Stage 1 WiFi + BT combo SoC chip with integrated dual-band PAs, LNAs, T/R switches, as well as a power management unit. The measured RX sensitivity of OFDM54M is -77.5dBm/ -77dBm in 2.4GHz and 5GHz, respectively. With the proposed broadband TX architecture, a high output power of 17.5dBm for 802.11ac Stage 1 VHT80 256QAM was achieved, and is extendable to the upcoming 802.11ac Stage2 VHT160. The maximum throughput achieved is 580Mbps in VHT80 MCS9 two-spatial stream mode, AWGN channel, with short GI. This chip occupies $27.8mm^{2}$ in 55nm 1P6M CMOS technology in which the MIMO WiFi RF and analog circuits occupies $7.7mm^{2}.$
Starting Page	225
Ending Page	228
File Size	814102
Page Count	4
File Format	PDF
ISBN	9781479938629
ISSN	15292517
e-ISBN	9781479938643
DOI	10.1109/RFIC.2014.6851704
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-06-01
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Switches MIMO System-on-chip Broadband communication IEEE 802.11 Standards Transceivers Radio frequency RF SoC WiFi IEEE 802.11ac MIMO SoC
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A 2×2 MIMO 802.11 b/g/n WLAN SOC in 55nm CMOS for AP/Router application

A 60nm WiFi/BT/GPS/FM combo connectivity SOC with integrated power amplifiers, virtual SP3T switch, and merged WiFi-BT transceiver

A dual-band 802.11abgn/ac transceiver with integrated PA and T/R switch in a digital noise controlled SoC

A 55nm, $0.6mm^{2}$ Bluetooth SoC integrated in cellular baseband chip with enhanced coexistence

A 32 nm SoC With Dual Core ATOM Processor and RF WiFi Transceiver

Dual-band CMOS transceiver with highly integrated front-end for 450Mb/s 802.11n systems

Double pole four throw CMOS switch in a transceiver of MIMO systems

A compact 5–6 GHz T/R module based on SiGe BiCMOS and SOI that enhances 256 QAM 802.11ac WLAN radio front-end designs

A 2.4GHz WLAN transceiver with fully-integrated highly-linear 1.8V 28.4dBm PA, 34dBm T/R switch, 240MS/s DAC, 320MS/s ADC, and DPLL in 32nm SoC CMOS

A 2×2 MIMO 802.11 abgn/ac WLAN SoC with integrated T/R switch and on-chip PA delivering VHT80 256QAM 17.5dBm in 55nm CMOS

Similar Documents

A 2×2 MIMO 802.11 b/g/n WLAN SOC in 55nm CMOS for AP/Router application

A 60nm WiFi/BT/GPS/FM combo connectivity SOC with integrated power amplifiers, virtual SP3T switch, and merged WiFi-BT transceiver

A dual-band 802.11abgn/ac transceiver with integrated PA and T/R switch in a digital noise controlled SoC

A 55nm, $0.6mm^{2}$ Bluetooth SoC integrated in cellular baseband chip with enhanced coexistence

A 32 nm SoC With Dual Core ATOM Processor and RF WiFi Transceiver

Dual-band CMOS transceiver with highly integrated front-end for 450Mb/s 802.11n systems

Double pole four throw CMOS switch in a transceiver of MIMO systems

A compact 5–6 GHz T/R module based on SiGe BiCMOS and SOI that enhances 256 QAM 802.11ac WLAN radio front-end designs

A 2.4GHz WLAN transceiver with fully-integrated highly-linear 1.8V 28.4dBm PA, 34dBm T/R switch, 240MS/s DAC, 320MS/s ADC, and DPLL in 32nm SoC CMOS

A 2×2 MIMO 802.11 abgn/ac WLAN SoC with integrated T/R switch and on-chip PA delivering VHT80 256QAM 17.5dBm in 55nm CMOS