NDLI: “Condition-based” dummy fill insertion method based on ECP and CMP predictive models

Content Provider	IEEE Xplore Digital Library
Author	Nitta, I. Kanazawa, Y. Fukuda, D. Shibuya, T. Idani, N. Ito, M. Yamasaki, O. Harada, N. Hiramoto, T.
Copyright Year	2010
Description	Author affiliation: Fujitsu Microelectronics Ltd., 2-10-23, Shin-Yokohama, Kohoku-ku, Japan (Idani, N.; Ito, M.; Yamasaki, O.; Harada, N.; Hiramoto, T.) \|\| Fujitsu Laboratories Ltd., 1-1, Kamikodanaka 4-chome, Nakahara-ku, Kawasaki, Japan (Nitta, I.; Kanazawa, Y.; Fukuda, D.) \|\| Fujitsu Laboratories of America, Inc., 1240 East Arques Avenue Sunnyvale, CA, USA (Shibuya, T.)
Abstract	Chemical Mechanical Polishing (CMP)-aware design has become important for reliability and yield. Recent work on predictive models for wafer surface planarity of Cu CMP has proven that the variation of wafer surface planarity is impacted by the metal perimeter in addition to the pattern density. Dummy fill insertion has been widely adopted to improve the CMP planarity in industrial design flows. However, conventional dummy fill insertion has been derived mainly to optimize the pattern density uniformity, which may worsen the CMP planarity because of missing impacts due to metal perimeter. In this paper, we propose; 1) a design of experiment (DOE) based method of evaluating the quality of fill insertion by using a CMP simulator which considers the impacts due to both pattern density and metal perimeter, and 2) a condition-based dummy fill insertion using the results of the proposed DOE method. Compared to the conventional pattern density driven rule-based fill insertion, the proposed method reduces the post-CMP Cu surface height variation by 24.3%. The metric of the metal perimeter may be applied to the model-based fill insertion methods, which will improve the planarity in the practical fill insertion flow.
Starting Page	198
Ending Page	205
File Size	426410
Page Count	8
File Format	PDF
ISBN	9781424464548
ISSN	19483295
e-ISBN	9781424464562
DOI	10.1109/ISQED.2010.5450461
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-03-22
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Predictive models Surface topography Approximation algorithms Laboratories US Department of Energy Semiconductor device modeling Manufacturing Integrated circuit interconnections Microelectronics Chemicals Design for Manufacturability Dummy fill Chemical Mechanical Polishing (CMP)
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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