NDLI: Slack-based approach for peak power reduction during transition fault testing

Content Provider	IEEE Xplore Digital Library
Author	Baby, M. Sarathi, V.
Copyright Year	2010
Description	Author affiliation: Dubai Circuit Design, Dubai Silicon Oasis, United Arab Emirates (Baby, M.; Sarathi, V.)
Abstract	Peak power consumption during test for the low power devices is a major concern [2, 3, 4]. Excessive peak power may result in test failures of functionally good devices. Huge peaks in the instantaneous power consumption will result in high rates of change of current (di/dt) causing adverse noise effects like VDD-drop and ground-bounce [1, 2, 3, 4]. Also, a high frequency of occurrence of high di/dt may cause severe decrease in the reliability of the circuit [1]. Hence the process of testing low power devices must be peak power aware. This paper provides a method to minimize the peak power during speed capture phase by partitioning the nodes into two zones based on their timing slacks. One of the zones contains the timing-critical nodes, while the other contains the non timing-critical ones. Each zone may be split into multiple bins. Test patterns are generated independently for each bin, targeting the nodes belonging to that bin alone, thus reducing the size of the target set. It is very important that the peak power consumed by the test patterns for each bin in the timing-critical zone is well within the tolerable limit. The bins in the non timing-critical zone may be allowed to have peak power consumptions very close to the limit or even marginally higher because the large positive slacks on these nodes will make up for the extra delay through the cells caused by VDD-drop/ground-bounce. This approach allows the designer to have a better control over each pattern and also helps to minimize the effects of high peak power and high di/dt.
Starting Page	577
Ending Page	581
File Size	407886
Page Count	5
File Format	PDF
ISBN	9781424464548
ISSN	19483295
e-ISBN	9781424464562
DOI	10.1109/ISQED.2010.5450516
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-03-22
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit testing Energy consumption Flip-flops Automatic test pattern generation Test pattern generators Delay Clocks Circuit faults Frequency Timing at-speed test and power budget DFT ATPG power-aware test capture cycle
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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