NDLI: Fixed outline multi-bend bus driven floorplanning

Content Provider	IEEE Xplore Digital Library
Author	Wenxu Sheng Sheqin Dong Yuliang Wu Goto, S.
Copyright Year	2010
Description	Author affiliation: Information Production and Systems, Waseda University, Kitakyushu, Japan, 808-0135 (Goto, S.) \|\| Department of Computer Science & Engineering, The Chinese University of Hong Kong, Shatin, N.T. China (Yuliang Wu) \|\| Tsinghua National Laboratory for Information Science & Technology, Tsinghua University, Beijing, China, 100084 (Wenxu Sheng; Sheqin Dong)
Abstract	Modern hierarchical SOC design flows need to deal with fixed-outline floorplanning under the interconnect constraints, in this paper, we address the problem of bus driven floorplanning in a fixed-outline area. Given a set of blocks, the bus specification, and the height and width of the chip area, a floorplan solution including bus routes and satisfying the outline constraint will be generated with the total floorplan area and total bus area minimized. The approach proposed in this paper is based on a deterministic algorithm Less Flexibility First (LFF), which runs in a fixed-outline area and packs hard blocks one after another with no drawbacks. In our approach, we put no limitation to the shape of the buses, and the processes block-packing and bus-packing are proceeding simultaneously. Experiment results show that under the constraint of fixed-outline, we can also obtain a good solution, with less dead space percentage and shorter run time, besides, for large test cases, our algorithm still works well.
Starting Page	632
Ending Page	637
File Size	246975
Page Count	6
File Format	PDF
ISBN	9781424464548
ISSN	19483295
e-ISBN	9781424464562
DOI	10.1109/ISQED.2010.5450512
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-03-22
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Routing Shape Testing Algorithm design and analysis Space technology Laboratories Information science Computer science Production systems Computational modeling Floorplanning Bus planning Fixed outline Deterministic algorithm
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in