NDLI: Coupling- and ECP-aware metal fill for improving layout uniformity in copper CMP

Content Provider	IEEE Xplore Digital Library
Author	Yu-Lun Co Hung-Ming Chen Yi-Kan Cheng
Copyright Year	2009
Description	Author affiliation: Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan (Yu-Lun Co; Hung-Ming Chen) \|\| Taiwan Semiconductor Manufacturing Company, Hsinchu, Taiwan (Yi-Kan Cheng)
Abstract	With feature sizes on chips shrinking at advanced process nodes, the difficulty in manufacturability and reliability of chips is extremely increasing. It has necessitated better planarization of chip surface topography to improve both functional and parametric yields. The common solution to minimize topography variation is to perform metal fills in empty spaces in the layout. However, these dummy metals will increase the capacitances between wires and then invoke delay and coupling/ crosstalk noise problems. Furthermore, the impact of ECP (electroplating) should be included in the copper CMP model in order to have accurate metal fill results. In this paper, we adopt and implement an approach to considering especially the key layout parameters that affect the post-ECP topography. We further apply a greedy-based method to place the floating dummy metals in the positions with minimal additional coupling capacitances. The experimental results are encouraging. Our method not only considers the thickness range of post-ECP, it can also add much less additional coupling capacitances over a density-driven metal fill method.
Starting Page	122
Ending Page	125
File Size	417921
Page Count	4
File Format	PDF
ISBN	9781424427819
DOI	10.1109/VDAT.2009.5158110
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-04-28
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Copper Surface topography Capacitance Semiconductor device modeling Planarization Crosstalk Manufacturing processes Delay Semiconductor device manufacture Wires
Content Type	Text
Resource Type	Article

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