NDLI: The iFlow design factory: evolving chip design from an art to a process, through adaptive resource management, and qualified data exchange

Content Provider	IEEE Xplore Digital Library
Author	Descamps, G.-E. Bagalkotkar, S. Ganesan, S. Subramaniam, S. Hingarh, H.
Copyright Year	2003
Description	Author affiliation: Silicon Access Networks, San Jose, CA, USA (Descamps, G.-E.; Bagalkotkar, S.; Ganesan, S.; Subramaniam, S.; Hingarh, H.)
Abstract	With advancing semiconductor technology, growing design complexities, companies have turned to a global design team to build their system on a chip (SoC). The major challenge is the capacity to scale infrastructure and methodology, along with ASIC design. Silicon Access Networks recently shipped for revenue from first silicon, a family of four high performance SoC products. These high-end networking products were designed in state-of-the-art 0.13 /spl mu/m process and collectively had about 750-million transistors and a variety of analog, digital and memory functional blocks to provide the industry's highest performance OC-192 Data Plane Processing solution. This paper describes some of the key aspects of Silicon Access Networks' design methodology that enabled to accomplish repeatable "first pass silicon" successes. We gained predictability in our chip design cycle through real-time visibility of the processes. Quality enhancing strategies were applied to the chip design cycles. Adaptive resource management, and qualified data exchange were the two main techniques. Multi site design teams working in different time zones may be a pitfall, or may allow for true 24/7 operation, depending on whether the right data and resources are available. Building such large designs in parallel requires efficient management of resources - machines, tools and users - in a transparent but truly global environment.
Sponsorship	IEEE Electron Device Soc. (EDS) IEEE Components, Packaging & Manuf. Technol. Soc. (CPMT) ACM ACM/sigDA
Starting Page	144
Ending Page	149
File Size	1225685
Page Count	6
File Format	PDF
ISBN	0769518818
DOI	10.1109/ISQED.2003.1194723
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-03-24
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Production facilities Chip scale packaging Art Resource management Silicon System-on-a-chip Application specific integrated circuits Product design Design methodology Team working
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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The iFlow design factory: evolving chip design from an art to a process, through adaptive resource management, and qualified data exchange