NDLI: Using integer equations for high level formal verification property checking

Content Provider	IEEE Xplore Digital Library
Author	Alizadeh, B. Kakoee, M.R.
Copyright Year	2003
Description	Author affiliation: Electr. & Comput. Eng., Tehran Univ., Iran (Alizadeh, B.)
Abstract	This paper describes the use of integer equations for high level modeling digital circuits for application of formal verification properties at this level. Most formal verification methods use BDDs, as a low level representation of a design. BDD operations require separation of data and control parts of a design and their implementation requires large CPU time and memory. In our method; a behavioral state machine is represented by a list of integer equations, and RT level properties are directly applied to this representation. This reduces the need for large BDD data structures and uses far less memory. Furthermore, this method is applied to circuits without having to separate their data and control sections. Integer equations are solved recursively by replacement and simplification operations. For this implementation, we use a canonical form of integer equations. This paper compares our results with those of the VIS verification tool that is a BDD based program.
Sponsorship	IEEE Electron Device Soc. (EDS) IEEE Components, Packaging & Manuf. Technol. Soc. (CPMT) ACM ACM/sigDA
Starting Page	69
Ending Page	74
File Size	251016
Page Count	6
File Format	PDF
ISBN	0769518818
DOI	10.1109/ISQED.2003.1194711
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-03-24
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Equations Formal verification Data structures Boolean functions Binary decision diagrams Data mining Logic design Logic circuits Flow graphs Digital circuits
Content Type	Text
Resource Type	Article

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