NDLI: The iFlow design factory infrastructure for a 17M-gate, 0.13/spl mu/m, 333MHz design [SoC design]

Content Provider	IEEE Xplore Digital Library
Author	Descamps, G.-E. Bagalkotkar, S.
Copyright Year	2003
Description	Author affiliation: Silicon Access Networks, San Jose, CA, USA (Descamps, G.-E.; Bagalkotkar, S.)
Abstract	To be able to meet the aggressive time-to-market requirements, and solve the challenges inherent to the multi-site design of large system-on-a-chips (SoCs), Silicon Access Networks had to evolve its art of chip design into an industrial process. This contribution describes a unique infrastructure which is quality-driven rather than time-committed. The chip design process is streamlined, visible, and measured, achieving predictability. By managing resources, Silicon Access Networks realized significant savings in time and maximized its return on investment (ROI). Bring-up and pre-production showed that first silicon met all its targets: power, speed, yield and complete functionality with no mask change. Four chips were designed using state-of-the-art 0.13 /spl mu/m technology and collectively represent 730-million transistors, implementing a variety of analog, digital, high-speed memory, and functional blocks.
Sponsorship	IEEE Solid-State Circuits Soc. IEEE Electron Devices Soc
Starting Page	27
Ending Page	34
File Size	664688
Page Count	8
File Format	PDF
ISBN	0780378423
DOI	10.1109/CICC.2003.1249353
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-09-24
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Production facilities Silicon Chip scale packaging Time to market System-on-a-chip Art Semiconductor device measurement Resource management Power system management Investments
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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The iFlow design factory: evolving chip design from an art to a process, through adaptive resource management, and qualified data exchange

Foundry 0.13 /spl mu/m CMOS modeling for MS//spl mu/wave SOC design at 10 GHz and beyond

Crosstalk delay analysis of a 0.13-/spl mu/m-node test chip and precise gate-level simulation technology

Analog front-end and power management integration on a 0.13 /spl mu/m CMOS ADSL SoC

Effects of assembly methodology on manufacturing-induced stresses in /spl mu/BGA packages

Design of 0.18 /spl mu/m CMOS test chip for package models and I/O characteristics verification

A 0.13 /spl mu/m BiCMOS technology featuring a 200/280 GHz (f/sub T//f/sub max/) SiGe HBT

/spl mu/I/O architecture for 0.13-/spl mu/m wide-voltage-range system-on-a-package (SoP) designs

A CMOS technology platform for 0.13 /spl mu/m generation SOC (system on a chip)

The iFlow design factory infrastructure for a 17M-gate, 0.13/spl mu/m, 333MHz design [SoC design]

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The iFlow design factory infrastructure for a 17M-gate, 0.13/spl mu/m, 333MHz design [SoC design]